library ieee;
use ieee.std_logic_1164.all;

entity buf4 is   --building the mux out of buffers for each input
  port( i : in std_logic_vector(4 downto 0);
        o : out std_logic_vector(4 downto 0);
        e : in std_logic
      );
end entity buf4;

architecture behav of buf4 is
  begin
    process (i, e)
    begin
      if( e = '1' ) then --when enabled, forward the input to the output
        o <= i;
      else
        o <= "ZZZZZ"; -- when not enabled, go to a high Z state
      end if;
      
    end process;
end behav;

library ieee;
use ieee.std_logic_1164.all;

entity muxS is
  port( i0, i1, i2, i3, i4, i5, i6 : in std_logic_vector(4 downto 0);
          sel : in std_logic_vector(2 downto 0);
          output : out std_logic_vector(4 downto 0)
       );
end entity muxS;

architecture struct of muxS is
  signal e0, e1, e2, e3, e4, e5, e6: std_logic;
  
  begin
    
    buf0 : entity work.buf4 
      port map( 
        i => i0, -- link inputs to the mux to an individual input to the buffer
        o => output, --link all outputs together
        e => e0  -- make an internal link  to enable signals
      );
     buf1 : entity work.buf4 
      port map( 
        i => i1,
        o => output,
        e => e1
      );
    buf2 : entity work.buf4 
      port map( 
        i => i2,
        o => output,
        e => e2
      );
    buf3 : entity work.buf4 
      port map( 
        i => i3,
        o => output,
        e => e3
      );
      buf4 : entity work.buf4 
      port map( 
        i => i4,
        o => output,
        e => e4
      );
      buf5 : entity work.buf4 
      port map( 
        i => i5,
        o => output,
        e => e5
      );
      buf6 : entity work.buf4 
      port map( 
        i => i6,
        o => output,
        e => e6
      );
      
    process ( i0, i1, i2, i3, i4, i5, i6, sel )
    begin
      
    e0 <= NOT sel(2) AND NOT sel(1) AND NOT sel(0);  -- intresting alternative way to define the enables rather than CASE
    e1 <= NOT sel(2) AND NOT sel(1) AND sel(0);
    e2 <= NOT sel(2) AND sel(1) AND NOT sel(0);
    e3 <= NOT sel(2) AND sel(1) AND sel(0);
    e4 <= sel(2) AND NOT sel(1) AND NOT sel(0);
    e5 <= sel(2) AND NOT sel(1) AND sel(0);
    e6 <= sel(2) AND sel(1) AND NOT sel(0);
      
    end process;
end struct;
library ieee;
use ieee.std_logic_1164.all;
entity test_bench_s is 
end entity test_bench_s; --Same design as before, with names of inputs and outputs modified to fit.
architecture behavior of test_bench_s is
    component muxS
      port( i0, i1, i2, i3, i4, i5, i6 : in std_logic_vector(4 downto 0);
          sel : in std_logic_vector(2 downto 0);
          output : out std_logic_vector(4 downto 0)
       );
  end component;
  signal i0, i1, i2, i3, i4, i5, i6 :  std_logic_vector(4 downto 0);
  signal sel :  std_logic_vector(2 downto 0);
  signal output :  std_logic_vector(4 downto 0);
  begin
      dut: muxS port map (
          i0 => i0,
          i1 => i1,
          i2 => i2,
          i3 => i3,
          i4 => i4,
          i5 => i5,
          i6 => i6,
          sel => sel,
          output => output
        );
        inputs: process
        begin
            i0 <= "10001"; 
            i1 <= "01010";
            i2 <= "10011";
            i3 <= "01100";
            i4 <= "10101";
            i5 <= "01110";
            i6 <= "10111";
            wait for 100 ns;
            
          end process;
         switch_input : process
         begin
            sel <= "000";
            wait for 10 ns;
            sel <= "001";
            wait for 10 ns;
            sel <= "010";
            wait for 10 ns;
            sel <= "011";
            wait for 10 ns;
            sel <= "100";
            wait for 10 ns;
            sel <= "101";
            wait for 10 ns;
            sel <= "110";
            wait for 10 ns; 
          end process;
        end;