library ieee; use ieee.std_logic_1164.all; entity mux57 is port( a,b,c,d,e,f,g: in std_logic_vector( 4 downto 0); --Inputs in the form of vectors for ease of coding and display on the wave plotter q: out std_logic_vector( 4 downto 0); -- Outputs in the same form for the same reasons sel : in std_logic_vector(2 downto 0) ); end entity mux57; architecture behav of mux57 is begin muxing : process is begin wait for 1 ns; --needed to avoid compiler warnings about infinte loops. case sel is when "000" => --based on the sel input, make the output 'q' equal to one of the inputs q <= a; when "001" => q <= b; when "010" => q <= c; when "011" => q <= d; when "100" => q <= e; when "101" => q <= f; when "110" => q <= g; when others => q <= "00000"; end case; end process muxing; end behav; library ieee; use ieee.std_logic_1164.all; entity test_bench is end entity test_bench; architecture behavior of test_bench is component mux57 port( a,b,c,d,e,f,g: in std_logic_vector( 4 downto 0); q: out std_logic_vector( 4 downto 0); sel : in std_logic_vector(2 downto 0) ); end component; signal a,b,c,d,e,f,g: std_logic_vector( 4 downto 0); signal q : std_logic_vector( 4 downto 0); signal sel : std_logic_vector(2 downto 0); begin dut: mux57 port map ( a => a, -- linking test bench outputs to mux input and outputs b => b, c => c, d => d, e => e, f => f, g => g, q => q, sel => sel ); inputs: process begin a <= "10001"; --setting each input to a unique value b <= "01010"; c <= "10011"; d <= "01100"; e <= "10101"; f <= "01110"; g <= "10111"; wait for 100 ns; end process; switch_input : process begin sel <= "000"; --switching between inputs to show functionality wait for 10 ns; sel <= "001"; wait for 10 ns; sel <= "010"; wait for 10 ns; sel <= "011"; wait for 10 ns; sel <= "100"; wait for 10 ns; sel <= "101"; wait for 10 ns; sel <= "110"; wait for 10 ns; end process; end;