fsm Project Status (10/21/2014 - 19:18:16)
Project File:	traffic.xise	Parser Errors:	No Errors
Module Name:	fsm	Implementation State:	Programming File Generated
Target Device:	xc3s500e-4fg320	Errors:	No Errors
Product Version:	ISE 14.6	Warnings:	1 Warning (0 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	40	9,312	1%
Number of 4 input LUTs	80	9,312	1%
Number of occupied Slices	61	4,656	1%
Number of Slices containing only related logic	61	61	100%
Number of Slices containing unrelated logic	0	61	0%
Total Number of 4 input LUTs	116	9,312	1%
Number used as logic	80
Number used as a route-thru	36
Number of bonded IOBs	9	232	3%
Number of BUFGMUXs	1	24	4%
Average Fanout of Non-Clock Nets	2.32

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue Oct 21 19:11:08 2014	0	1 Warning (0 new)	1 Info (0 new)
Translation Report	Current	Tue Oct 21 19:17:26 2014	0	0	0
Map Report	Current	Tue Oct 21 19:17:34 2014	0	0	2 Infos (0 new)
Place and Route Report	Current	Tue Oct 21 19:17:52 2014	0	0	2 Infos (0 new)
Power Report
Post-PAR Static Timing Report	Current	Tue Oct 21 19:17:56 2014	0	0	6 Infos (0 new)
Bitgen Report	Current	Tue Oct 21 19:18:06 2014	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Out of Date	Tue Oct 14 20:39:16 2014
WebTalk Report	Current	Tue Oct 21 19:18:08 2014
WebTalk Log File	Current	Tue Oct 21 19:18:14 2014

Date Generated: 10/21/2014 - 19:18:17