Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.6 (ISE) - P.68d Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s500e
Project ID (random number) 82f0d94137d34679837fecd9ed93309e.D1B765AE483C4581B9A3E1789B76909B.6 Target Package: fg320
Registration ID 174534306_174123213_210564973_342 Target Speed: -4
Date Generated 2014-10-14T20:35:11 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 32-bit adder=1
 Comparators=7
  • 32-bit comparator greatequal=2
  • 32-bit comparator lessequal=1
  • 4-bit comparator greater=3
  • 4-bit comparator lessequal=1
 Counters=1
  • 4-bit up counter=1
 FSMs=1 Registers=33
  • Flip-Flops=33
 		MiscellaneousStatistics
  • AGG_BONDED_IO=7
  • AGG_IO=7
  • AGG_SLICE=61
  • NUM_4_INPUT_LUT=116
  • NUM_BONDED_IBUF=1
  • NUM_BONDED_IOB=6
  • NUM_BUFGMUX=1
  • NUM_CYMUX=62
  • NUM_LUT_RT=35
  • NUM_MULTAND=1
  • NUM_SLICEL=61
  • NUM_SLICE_FF=40
  • NUM_XOR=32
 		NetStatistics
  • NumNets_Active=129
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=25
  • NumNodesOfType_Active_CNTRLPIN=7
  • NumNodesOfType_Active_DOUBLE=99
  • NumNodesOfType_Active_DUMMY=235
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_GLOBAL=7
  • NumNodesOfType_Active_HFULLHEX=1
  • NumNodesOfType_Active_HUNIHEX=3
  • NumNodesOfType_Active_INPUT=274
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_OMUX=92
  • NumNodesOfType_Active_OUTPUT=122
  • NumNodesOfType_Active_PREBXBY=42
  • NumNodesOfType_Active_VFULLHEX=4
  • NumNodesOfType_Active_VLONG=2
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=3
  • NumNodesOfType_Vcc_PREBXBY=3
  • NumNodesOfType_Vcc_VCCOUT=4
 SiteStatistics
  • IBUF-DIFFM=1
  • IOB-DIFFM=2
  • IOB-DIFFS=4
  • SLICEL-SLICEM=23
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=1
  • IBUF_INBUF=1
  • IBUF_PAD=1
  • IOB=6
  • IOB_OUTBUF=6
  • IOB_PAD=6
  • SLICEL=61
  • SLICEL_C1VDD=8
  • SLICEL_C2VDD=6
  • SLICEL_CYMUXF=32
  • SLICEL_CYMUXG=30
  • SLICEL_F=59
  • SLICEL_F5MUX=3
  • SLICEL_FAND=1
  • SLICEL_FFX=22
  • SLICEL_FFY=18
  • SLICEL_G=57
  • SLICEL_GNDF=23
  • SLICEL_GNDG=24
  • SLICEL_XORF=16
  • SLICEL_XORG=16
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:1]
 IOB
  • O1=[O1_INV:0] [O1:6]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:6]
 IOB_PAD
  • DRIVEATTRBOX=[12:6]
  • IOATTRBOX=[LVCMOS25:6]
  • SLEW=[SLOW:6]
 SLICEL
  • BX=[BX_INV:1] [BX:6]
  • BY=[BY:1] [BY_INV:0]
  • CE=[CE:2] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:29]
  • CLK=[CLK:25] [CLK_INV:0]
  • SR=[SR:5] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:32] [0_INV:0]
  • 1=[1_INV:0] [1:32]
 SLICEL_CYMUXG
  • 0=[0:30] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:3] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:2] [CE_INV:0]
  • CK=[CK:22] [CK_INV:0]
  • D=[D:21] [D_INV:1]
  • FFX_INIT_ATTR=[INIT0:22]
  • FFX_SR_ATTR=[SRLOW:21] [SRHIGH:1]
  • LATCH_OR_FF=[FF:22]
  • SR=[SR:3] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:19] [SYNC:3]
 SLICEL_FFY
  • CE=[CE:2] [CE_INV:0]
  • CK=[CK:18] [CK_INV:0]
  • D=[D:18] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:18]
  • FFY_SR_ATTR=[SRLOW:18]
  • LATCH_OR_FF=[FF:18]
  • SR=[SR:4] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:14] [SYNC:4]
 SLICEL_XORF
  • 1=[1_INV:0] [1:16]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 IBUF
  • I=1
  • PAD=1
 IBUF_INBUF
  • IN=1
  • OUT=1
 IBUF_PAD
  • PAD=1
 IOB
  • O1=6
  • PAD=6
 IOB_OUTBUF
  • IN=6
  • OUT=6
 IOB_PAD
  • PAD=6
 SLICEL
  • BX=7
  • BY=1
  • CE=2
  • CIN=29
  • CLK=25
  • COUT=30
  • F1=59
  • F2=39
  • F3=13
  • F4=9
  • G1=57
  • G2=37
  • G3=13
  • G4=7
  • SR=5
  • X=26
  • XB=1
  • XQ=22
  • Y=23
  • YQ=18
 SLICEL_C1VDD
  • 1=8
 SLICEL_C2VDD
  • 1=6
 SLICEL_CYMUXF
  • 0=32
  • 1=32
  • OUT=32
  • S0=32
 SLICEL_CYMUXG
  • 0=30
  • 1=30
  • OUT=30
  • S0=30
 SLICEL_F
  • A1=59
  • A2=39
  • A3=13
  • A4=9
  • D=59
 SLICEL_F5MUX
  • F=3
  • G=3
  • OUT=3
  • S0=3
 SLICEL_FAND
  • 0=1
  • 1=1
  • O=1
 SLICEL_FFX
  • CE=2
  • CK=22
  • D=22
  • Q=22
  • SR=3
 SLICEL_FFY
  • CE=2
  • CK=18
  • D=18
  • Q=18
  • SR=4
 SLICEL_G
  • A1=57
  • A2=37
  • A3=13
  • A4=7
  • D=57
 SLICEL_GNDF
  • 0=23
 SLICEL_GNDG
  • 0=24
 SLICEL_XORF
  • 0=16
  • 1=16
  • O=16
 SLICEL_XORG
  • 0=16
  • 1=16
  • O=16
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 130 104 0 0 0 0 0
bitgen 159 159 0 0 0 0 0
libgen 1 1 0 0 0 0 0
map 219 209 0 0 0 0 0
netgen 2 2 0 0 0 0 0
ngc2edif 78 78 0 0 0 0 0
ngcbuild 3 3 0 0 0 0 0
ngdbuild 233 233 0 0 0 0 0
par 209 192 16 0 0 0 0
platgen 3 3 0 0 0 0 0
psf2Edward 2 2 0 0 0 0 0
trce 191 191 0 0 0 0 0
xdsgen 2 2 0 0 0 0 0
xps 3 3 0 0 0 0 0
xst 460 452 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/ite_c_overview.htm ( 1 ) /doc/usenglish/isehelp/pn_db_nsw_associate_source.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/test PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2014-10-14T19:02:44 PROP_intWbtProjectID=D1B765AE483C4581B9A3E1789B76909B
PROP_intWbtProjectIteration=6 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.test PROP_AutoTop=true
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s500e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=fg320
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=4
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=33 NGDBUILD_NUM_FDR=2 NGDBUILD_NUM_FDRE=4
NGDBUILD_NUM_FDS=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_INV=6 NGDBUILD_NUM_LUT1=34
NGDBUILD_NUM_LUT2=49 NGDBUILD_NUM_LUT3=11 NGDBUILD_NUM_LUT4=16 NGDBUILD_NUM_MULT_AND=1
NGDBUILD_NUM_MUXCY=62 NGDBUILD_NUM_MUXF5=3 NGDBUILD_NUM_OBUF=6 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=32
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=33 NGDBUILD_NUM_FDR=2 NGDBUILD_NUM_FDRE=4
NGDBUILD_NUM_FDS=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=6
NGDBUILD_NUM_LUT1=34 NGDBUILD_NUM_LUT2=49 NGDBUILD_NUM_LUT3=11 NGDBUILD_NUM_LUT4=16
NGDBUILD_NUM_MULT_AND=1 NGDBUILD_NUM_MUXCY=62 NGDBUILD_NUM_MUXF5=3 NGDBUILD_NUM_OBUF=6
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=32
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s500e-4-fg320 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=ieee
Fuse Resource Usage=577 ms, 35900 KB
Total Signals=11
Total Nets=9
Total Blocks=4
Total Processes=4
Total Simulation Time=1 us
Simulation Resource Usage=0.218401 sec, 1117786 KB
Simulation Mode=gui
Hardware CoSim=0