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-- Company: 
-- Engineer:
--
-- Create Date:   20:55:40 09/16/2014
-- Design Name:   
-- Module Name:   C:/Users/Student/Desktop/Workspace/hamming/hamming_test.vhd
-- Project Name:  hamming
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: hamming
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY hamming_test IS
END hamming_test;
 
ARCHITECTURE behavior OF hamming_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT hamming
    PORT(
         Bin : IN  std_logic_vector(4 downto 1);
         Bout : OUT  std_logic_vector(4 downto 1)
        );
    END COMPONENT;
    

   --Inputs
   signal Bin : std_logic_vector(4 downto 1) := (others => '0');

 	--Outputs
   signal Bout : std_logic_vector(4 downto 1);
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: hamming PORT MAP (
          Bin => Bin,
          Bout => Bout
        );
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 10 ns;	

		Bin <= "0001";
		
		wait for 10 ns;
		
		Bin <= "0010";
		
		wait for 10 ns;
		
		Bin <= "0100";
		
		wait for 10 ns;
		
		Bin <= "1000";
		
		wait for 10 ns;
		
		Bin <= "0011";
		
		wait for 10 ns;
		
		Bin <= "0111";
		
		wait for 10 ns;
		
		Bin <= "1111";

      -- insert stimulus here 

      wait;
   end process;

END;