Project Statistics |
PROPEXT_xilxSynthMaxFanout_virtex2=100000 |
PROP_Board=Spartan-3E Starter Board |
PROP_Enable_Message_Filtering=false |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/hamming_test |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_intProjectCreationTimestamp=2014-09-16T19:09:41 |
PROP_intWbtProjectID=06B4C5625DC64D0DB8FBD5CF81B6F55B |
PROP_intWbtProjectIteration=10 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_selectedSimRootSourceNode_behav=work.hamming_test |
PROP_xilxBitgStart_IntDone=true |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3E |
PROP_ibiswriterOutputFile=hamming_encoder4 |
PROP_DevDevice=xc3s500e |
PROP_DevFamilyPMName=spartan3e |
PROP_DevPackage=fg320 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=VHDL |
PROP_netgenPostMapSimModelName=hamming_encoder4_map.vhd |
PROP_netgenPostParSimModelName=hamming_encoder4_timesim.vhd |
PROP_netgenPostSynthesisSimModelName=hamming_encoder4_synthesis.vhd |
PROP_netgenPostXlateSimModelName=hamming_encoder4_translate.vhd |
PROP_netgenRenameTopLevEntTo=hamming_encoder4 |
FILE_UCF=1 |
FILE_VHDL=8 |