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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:23:07 09/16/2014 
-- Design Name: 
-- Module Name:    hamming_encoder - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity encoder is
	Port ( D : in  STD_LOGIC_VECTOR(4 downto 1);
	       B : out  STD_LOGIC_VECTOR(7 downto 1)
);
end encoder;

architecture enc_arch of encoder is
begin
	B(1) <= D(1) xor D(2) xor D(4);
	B(2) <= D(1) xor D(3) xor D(4);
	B(3) <= D(1);
	B(4) <= D(2) xor D(3) xor D(4);
	B(5) <= D(2);
	B(6) <= D(3);
	B(7) <= D(4);
end enc_arch;