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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:38:59 09/16/2014 
-- Design Name: 
-- Module Name:    hamming - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity hamming is
    Port ( Bin : in  STD_LOGIC_VECTOR (4 downto 1);
           Bout : out  STD_LOGIC_VECTOR (4 downto 1);
			  SW : in STD_LOGIC_VECTOR (7 downto 1) );
end hamming;

architecture Behavioral of hamming is

	signal B, BS : STD_LOGIC_VECTOR(7 downto 1);
	signal C : STD_LOGIC_VECTOR(3 downto 1);

	component encoder
	Port ( d : in  STD_LOGIC_VECTOR(4 downto 1);
	       b : out  STD_LOGIC_VECTOR(7 downto 1) );
	end component;
	
	component decoder
	Port ( b : in  STD_LOGIC_VECTOR(7 downto 1);
	       c : out  STD_LOGIC_VECTOR(3 downto 1) );
	end component;
	
	component corrector
	Port ( b : in  STD_LOGIC_VECTOR(7 downto 1);
	       c : in  STD_LOGIC_VECTOR(3 downto 1);
	       o : out STD_LOGIC_VECTOR(4 downto 1) );
	end component;

begin

	encoder_0: encoder
		port map (
			d => Bin,
			b => B
		);
		
	BS <= B XOR SW;
		
	decoder_0: decoder
		port map (
			b => BS,
			c => C
		);
	corrector_0: corrector
		port map (
			b => BS,
			c => C,
			o => Bout
		);
end Behavioral;