encoder Project Status
Project File:	hamming.xise	Parser Errors:	No Errors
Module Name:	encoder	Implementation State:	Placed and Routed
Target Device:	xc3s500e-4fg320	Errors:	No Errors
Product Version:	ISE 14.6	Warnings:	No Warnings
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of 4 input LUTs	3	9,312	1%
Number of occupied Slices	2	4,656	1%
Number of Slices containing only related logic	2	2	100%
Number of Slices containing unrelated logic	0	2	0%
Total Number of 4 input LUTs	3	9,312	1%
Number of bonded IOBs	11	232	4%
Average Fanout of Non-Clock Nets	2.29

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue Sep 16 20:19:37 2014	0	0	0
Translation Report	Current	Tue Sep 16 20:19:43 2014	0	0	0
Map Report	Current	Tue Sep 16 20:19:48 2014	0	0	2 Infos (0 new)
Place and Route Report	Current	Tue Sep 16 20:19:57 2014	0	0	1 Info (0 new)
Power Report
Post-PAR Static Timing Report	Current	Tue Sep 16 20:20:00 2014	0	0	6 Infos (0 new)
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Current	Tue Sep 16 20:37:03 2014

Date Generated: 09/16/2014 - 20:39:25