LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
 
ENTITY encryptor_test IS
END encryptor_test;
 
ARCHITECTURE behavior OF encryptor_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT encryptor
    PORT(
         SEED : IN  std_logic_vector(7 downto 0);
         MIN : IN  std_logic_vector(7 downto 0);
         MOUT : OUT  std_logic_vector(7 downto 0);
         CLK : IN  std_logic;
         LOAD : IN  std_logic;
			EN : IN std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal SEED : std_logic_vector(7 downto 0) := x"34";
   signal MIN : std_logic_vector(7 downto 0) := (others => '0');
   signal CLK : std_logic := '0';
   signal LOAD : std_logic := '1';
	signal EN : std_logic := '0';

 	--Outputs
   signal MOUT : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: encryptor PORT MAP (
          SEED => SEED,
          MIN => MIN,
          MOUT => MOUT,
          CLK => CLK,
          LOAD => LOAD,
			 EN => EN
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for CLK_period*10;

      -- insert stimulus here 
		
		SEED <= x"FF";
		
		wait for 10 ns;
		
		EN <= '1';
		SEED <= x"34";

		wait for 10 ns;
		
		LOAD <= '0';
		MIN <= x"67";
		
		wait for 10 ns;
		
		MIN <= x"6A";
		
		wait for 10 ns;
		
		MIN <= x"D1";
		
		wait for 10 ns;
		
		EN <= '0';
		
      wait;
   end process;

END;