Project Statistics |
PROPEXT_xilxSynthMaxFanout_virtex2=100000 |
PROP_Board=Spartan-3E Starter Board |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/encryptor_test |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2014-11-03T20:32:44 |
PROP_intWbtProjectID=9F44150BE75B68B91718BC94069290B2 |
PROP_intWbtProjectIteration=2 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.encryptor_test |
PROP_xilxBitgStart_IntDone=true |
PROP_AutoTop=false |
PROP_DevFamily=Spartan3E |
PROP_DevDevice=xc3s500e |
PROP_DevFamilyPMName=spartan3e |
PROP_DevPackage=fg320 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=Verilog |
FILE_VHDL=3 |