encryptor Project Status (11/03/2014 - 21:59:02)
Project File: Encryptor.xise Parser Errors: No Errors
Module Name: encryptor Implementation State: Programming File Generated
Target Device: xc3s500e-4fg320
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
3 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 16 9,312 1%  
Number of 4 input LUTs 33 9,312 1%  
Number of occupied Slices 17 4,656 1%  
    Number of Slices containing only related logic 17 17 100%  
    Number of Slices containing unrelated logic 0 17 0%  
Total Number of 4 input LUTs 33 9,312 1%  
Number of bonded IOBs 35 232 15%  
Average Fanout of Non-Clock Nets 2.20      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Nov 3 21:58:34 201401 Warning (0 new)1 Info (0 new)
Translation ReportCurrentMon Nov 3 21:58:40 2014000
Map ReportCurrentMon Nov 3 21:58:46 201401 Warning (0 new)2 Infos (0 new)
Place and Route ReportCurrentMon Nov 3 21:58:55 2014002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Nov 3 21:58:57 2014006 Infos (0 new)
Bitgen ReportCurrentMon Nov 3 21:59:00 201401 Warning (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateMon Nov 3 21:41:05 2014
WebTalk ReportCurrentMon Nov 3 21:59:01 2014
WebTalk Log FileCurrentMon Nov 3 21:59:02 2014

Date Generated: 11/03/2014 - 21:59:02