-------------------------------------------------------------------------------- Release 14.7 Trace (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml encryptor.twx encryptor.ncd -o encryptor.twr encryptor.pcf Design file: encryptor.ncd Physical constraint file: encryptor.pcf Device,package,speed: xc3s500e,fg320,-4 (PRODUCTION 1.27 2013-10-13) Report level: verbose report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:2698 - No timing constraints found, doing default enumeration. INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation. INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Setup/Hold to clock CLK ------------+------------+------------+------------------+--------+ |Max Setup to|Max Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ LOAD | 0.293(R)| 2.124(R)|lfsr_0/clk_i | 0.000| SEED<0> | -0.157(R)| 2.260(R)|lfsr_0/clk_i | 0.000| SEED<1> | -0.332(R)| 2.066(R)|lfsr_0/clk_i | 0.000| SEED<2> | -0.948(R)| 2.650(R)|lfsr_0/clk_i | 0.000| SEED<3> | -0.173(R)| 1.984(R)|lfsr_0/clk_i | 0.000| SEED<4> | -0.222(R)| 2.148(R)|lfsr_0/clk_i | 0.000| SEED<5> | 0.119(R)| 2.125(R)|lfsr_0/clk_i | 0.000| SEED<6> | 0.087(R)| 1.852(R)|lfsr_0/clk_i | 0.000| SEED<7> | 0.047(R)| 1.934(R)|lfsr_0/clk_i | 0.000| ------------+------------+------------+------------------+--------+ Setup/Hold to clock EN ------------+------------+------------+------------------+--------+ |Max Setup to|Max Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ LOAD | 0.312(R)| 2.099(R)|lfsr_0/clk_i | 0.000| SEED<0> | -0.138(R)| 2.235(R)|lfsr_0/clk_i | 0.000| SEED<1> | -0.313(R)| 2.041(R)|lfsr_0/clk_i | 0.000| SEED<2> | -0.929(R)| 2.625(R)|lfsr_0/clk_i | 0.000| SEED<3> | -0.154(R)| 1.959(R)|lfsr_0/clk_i | 0.000| SEED<4> | -0.203(R)| 2.123(R)|lfsr_0/clk_i | 0.000| SEED<5> | 0.138(R)| 2.100(R)|lfsr_0/clk_i | 0.000| SEED<6> | 0.106(R)| 1.827(R)|lfsr_0/clk_i | 0.000| SEED<7> | 0.066(R)| 1.909(R)|lfsr_0/clk_i | 0.000| ------------+------------+------------+------------------+--------+ Clock CLK to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ CRYPT<0> | 11.184(R)|lfsr_0/clk_i | 0.000| CRYPT<1> | 11.235(R)|lfsr_0/clk_i | 0.000| CRYPT<2> | 10.593(R)|lfsr_0/clk_i | 0.000| CRYPT<3> | 10.225(R)|lfsr_0/clk_i | 0.000| CRYPT<4> | 9.900(R)|lfsr_0/clk_i | 0.000| CRYPT<5> | 10.752(R)|lfsr_0/clk_i | 0.000| CRYPT<6> | 10.087(R)|lfsr_0/clk_i | 0.000| CRYPT<7> | 10.291(R)|lfsr_0/clk_i | 0.000| MOUT<0> | 12.017(R)|lfsr_0/clk_i | 0.000| MOUT<1> | 11.622(R)|lfsr_0/clk_i | 0.000| MOUT<2> | 11.712(R)|lfsr_0/clk_i | 0.000| MOUT<3> | 10.916(R)|lfsr_0/clk_i | 0.000| MOUT<4> | 10.572(R)|lfsr_0/clk_i | 0.000| MOUT<5> | 11.602(R)|lfsr_0/clk_i | 0.000| MOUT<6> | 10.973(R)|lfsr_0/clk_i | 0.000| MOUT<7> | 10.845(R)|lfsr_0/clk_i | 0.000| ------------+------------+------------------+--------+ Clock EN to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ CRYPT<0> | 11.159(R)|lfsr_0/clk_i | 0.000| CRYPT<1> | 11.210(R)|lfsr_0/clk_i | 0.000| CRYPT<2> | 10.568(R)|lfsr_0/clk_i | 0.000| CRYPT<3> | 10.200(R)|lfsr_0/clk_i | 0.000| CRYPT<4> | 9.875(R)|lfsr_0/clk_i | 0.000| CRYPT<5> | 10.727(R)|lfsr_0/clk_i | 0.000| CRYPT<6> | 10.062(R)|lfsr_0/clk_i | 0.000| CRYPT<7> | 10.266(R)|lfsr_0/clk_i | 0.000| MOUT<0> | 11.992(R)|lfsr_0/clk_i | 0.000| MOUT<1> | 11.597(R)|lfsr_0/clk_i | 0.000| MOUT<2> | 11.687(R)|lfsr_0/clk_i | 0.000| MOUT<3> | 10.891(R)|lfsr_0/clk_i | 0.000| MOUT<4> | 10.547(R)|lfsr_0/clk_i | 0.000| MOUT<5> | 11.577(R)|lfsr_0/clk_i | 0.000| MOUT<6> | 10.948(R)|lfsr_0/clk_i | 0.000| MOUT<7> | 10.820(R)|lfsr_0/clk_i | 0.000| ------------+------------+------------------+--------+ Clock to Setup on destination clock CLK ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ CLK | 2.620| | | | EN | 2.620| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock EN ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ CLK | 2.620| | | | EN | 2.620| | | | ---------------+---------+---------+---------+---------+ Pad to Pad ---------------+---------------+---------+ Source Pad |Destination Pad| Delay | ---------------+---------------+---------+ MIN<0> |CRYPT<0> | 6.169| MIN<0> |MOUT<0> | 6.731| MIN<1> |CRYPT<1> | 5.975| MIN<1> |MOUT<1> | 6.297| MIN<2> |CRYPT<2> | 6.008| MIN<2> |MOUT<2> | 6.729| MIN<3> |CRYPT<3> | 6.034| MIN<3> |MOUT<3> | 6.569| MIN<4> |CRYPT<4> | 6.277| MIN<4> |MOUT<4> | 6.752| MIN<5> |CRYPT<5> | 6.633| MIN<5> |MOUT<5> | 6.971| MIN<6> |CRYPT<6> | 6.169| MIN<6> |MOUT<6> | 6.843| MIN<7> |CRYPT<7> | 6.717| MIN<7> |MOUT<7> | 6.919| ---------------+---------------+---------+ Analysis completed Mon Nov 3 21:58:57 2014 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 347 MB