Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.6 (ISE) - P.68d Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s500e
Project ID (random number) 82f0d94137d34679837fecd9ed93309e.9F217248BC284FD2A2AA1EBDCFD0AC2B.1 Target Package: fg320
Registration ID 174534306_174123213_210564973_342 Target Speed: -4
Date Generated 2014-10-07T20:24:12 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 32-bit adder=1
 Comparators=3
  • 32-bit comparator greatequal=2
  • 32-bit comparator lessequal=1
 FSMs=1 Registers=33
  • Flip-Flops=33
 		MiscellaneousStatistics
  • AGG_BONDED_IO=6
  • AGG_IO=6
  • AGG_SLICE=52
  • NUM_4_INPUT_LUT=98
  • NUM_BONDED_IBUF=3
  • NUM_BONDED_IOB=3
  • NUM_BUFGMUX=1
  • NUM_CYMUX=62
  • NUM_LUT_RT=35
  • NUM_MULTAND=1
  • NUM_SLICEL=52
  • NUM_SLICE_FF=36
  • NUM_XOR=32
 		NetStatistics
  • NumNets_Active=114
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=22
  • NumNodesOfType_Active_CNTRLPIN=3
  • NumNodesOfType_Active_DOUBLE=48
  • NumNodesOfType_Active_DUMMY=177
  • NumNodesOfType_Active_DUMMYESC=3
  • NumNodesOfType_Active_GLOBAL=12
  • NumNodesOfType_Active_HFULLHEX=1
  • NumNodesOfType_Active_HLONG=1
  • NumNodesOfType_Active_HUNIHEX=2
  • NumNodesOfType_Active_INPUT=209
  • NumNodesOfType_Active_IOBOUTPUT=3
  • NumNodesOfType_Active_OMUX=90
  • NumNodesOfType_Active_OUTPUT=106
  • NumNodesOfType_Active_PREBXBY=17
  • NumNodesOfType_Active_VFULLHEX=3
  • NumNodesOfType_Active_VLONG=1
  • NumNodesOfType_Active_VUNIHEX=11
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=3
  • NumNodesOfType_Vcc_PREBXBY=3
  • NumNodesOfType_Vcc_VCCOUT=4
 SiteStatistics
  • IBUF-DIFFM=1
  • IOB-DIFFM=2
  • IOB-DIFFS=1
  • SLICEL-SLICEM=24
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=3
  • IBUF_INBUF=3
  • IBUF_PAD=3
  • IOB=3
  • IOB_OUTBUF=3
  • IOB_PAD=3
  • SLICEL=52
  • SLICEL_C1VDD=8
  • SLICEL_C2VDD=6
  • SLICEL_CYMUXF=32
  • SLICEL_CYMUXG=30
  • SLICEL_F=50
  • SLICEL_FAND=1
  • SLICEL_FFX=18
  • SLICEL_FFY=18
  • SLICEL_G=48
  • SLICEL_GNDF=23
  • SLICEL_GNDG=24
  • SLICEL_XORF=16
  • SLICEL_XORG=16
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:3]
 IOB
  • O1=[O1_INV:0] [O1:3]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:3]
 IOB_PAD
  • DRIVEATTRBOX=[12:3]
  • IOATTRBOX=[LVCMOS25:3]
  • SLEW=[SLOW:3]
 SLICEL
  • BX=[BX_INV:0] [BX:3]
  • BY=[BY:1] [BY_INV:0]
  • CIN=[CIN_INV:0] [CIN:29]
  • CLK=[CLK:22] [CLK_INV:0]
  • SR=[SR:3] [SR_INV:0]
 SLICEL_CYMUXF
  • 0=[0:32] [0_INV:0]
  • 1=[1_INV:0] [1:32]
 SLICEL_CYMUXG
  • 0=[0:30] [0_INV:0]
 SLICEL_FFX
  • CK=[CK:18] [CK_INV:0]
  • D=[D:18] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:18]
  • FFX_SR_ATTR=[SRLOW:18]
  • LATCH_OR_FF=[FF:18]
  • SR=[SR:1] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:17] [SYNC:1]
 SLICEL_FFY
  • CK=[CK:18] [CK_INV:0]
  • D=[D:18] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:18]
  • FFY_SR_ATTR=[SRLOW:18]
  • LATCH_OR_FF=[FF:18]
  • SR=[SR:3] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:15] [SYNC:3]
 SLICEL_XORF
  • 1=[1_INV:0] [1:16]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 IBUF
  • I=3
  • PAD=3
 IBUF_INBUF
  • IN=3
  • OUT=3
 IBUF_PAD
  • PAD=3
 IOB
  • O1=3
  • PAD=3
 IOB_OUTBUF
  • IN=3
  • OUT=3
 IOB_PAD
  • PAD=3
 SLICEL
  • BX=3
  • BY=1
  • CIN=29
  • CLK=22
  • COUT=30
  • F1=50
  • F2=30
  • F3=7
  • F4=3
  • G1=48
  • G2=28
  • G3=7
  • G4=3
  • SR=3
  • X=20
  • XB=1
  • XQ=18
  • Y=17
  • YQ=18
 SLICEL_C1VDD
  • 1=8
 SLICEL_C2VDD
  • 1=6
 SLICEL_CYMUXF
  • 0=32
  • 1=32
  • OUT=32
  • S0=32
 SLICEL_CYMUXG
  • 0=30
  • 1=30
  • OUT=30
  • S0=30
 SLICEL_F
  • A1=50
  • A2=30
  • A3=7
  • A4=3
  • D=50
 SLICEL_FAND
  • 0=1
  • 1=1
  • O=1
 SLICEL_FFX
  • CK=18
  • D=18
  • Q=18
  • SR=1
 SLICEL_FFY
  • CK=18
  • D=18
  • Q=18
  • SR=3
 SLICEL_G
  • A1=48
  • A2=28
  • A3=7
  • A4=3
  • D=48
 SLICEL_GNDF
  • 0=23
 SLICEL_GNDG
  • 0=24
 SLICEL_XORF
  • 0=16
  • 1=16
  • O=16
 SLICEL_XORG
  • 0=16
  • 1=16
  • O=16
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 126 100 0 0 0 0 0
bitgen 154 154 0 0 0 0 0
libgen 1 1 0 0 0 0 0
map 212 202 0 0 0 0 0
netgen 2 2 0 0 0 0 0
ngc2edif 76 76 0 0 0 0 0
ngcbuild 3 3 0 0 0 0 0
ngdbuild 226 226 0 0 0 0 0
par 202 186 16 0 0 0 0
platgen 3 3 0 0 0 0 0
psf2Edward 2 2 0 0 0 0 0
trce 185 185 0 0 0 0 0
xdsgen 2 2 0 0 0 0 0
xps 3 3 0 0 0 0 0
xst 432 424 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/ite_c_overview.htm ( 1 ) /doc/usenglish/isehelp/pn_db_nsw_associate_source.htm ( 1 )
 
Project Statistics
PROP_Board=Spartan-3E Starter Board PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/fsm_test
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2014-10-07T19:39:57
PROP_intWbtProjectID=9F217248BC284FD2A2AA1EBDCFD0AC2B PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_selectedSimRootSourceNode_behav=work.fsm_test
PROP_AutoTop=true PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s500e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=fg320 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VHDL=3
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=32 NGDBUILD_NUM_FDR=4 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_INV=5 NGDBUILD_NUM_LUT1=34 NGDBUILD_NUM_LUT2=43
NGDBUILD_NUM_LUT3=9 NGDBUILD_NUM_LUT4=6 NGDBUILD_NUM_MULT_AND=1 NGDBUILD_NUM_MUXCY=62
NGDBUILD_NUM_OBUF=3 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=32
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=32 NGDBUILD_NUM_FDR=4 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=5 NGDBUILD_NUM_LUT1=34
NGDBUILD_NUM_LUT2=43 NGDBUILD_NUM_LUT3=9 NGDBUILD_NUM_LUT4=6 NGDBUILD_NUM_MULT_AND=1
NGDBUILD_NUM_MUXCY=62 NGDBUILD_NUM_OBUF=3 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=32
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s500e-4-fg320 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5