FSM Project Status (10/07/2014 - 20:24:21)
Project File: turn_signal.xise Parser Errors: No Errors
Module Name: selectable_clock Implementation State: Programming File Not Generated
Target Device: xc3s500e-4fg320
  • Errors:
  
Product Version:ISE 14.6
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentTue Oct 7 20:24:14 2014
WebTalk Log FileCurrentTue Oct 7 20:24:22 2014

Date Generated: 10/07/2014 - 20:24:21