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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:41:10 10/07/2014 
-- Design Name: 
-- Module Name:    FSM - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FSM is
    Port ( l : in  STD_LOGIC;
           r : in  STD_LOGIC;
           ro : out  STD_LOGIC;
           lo : out  STD_LOGIC;
           ho : out  STD_LOGIC;
			  clk_in : in STD_LOGIC);
end FSM;

architecture Behavioral of FSM is

	type state is (idle, sl, sr, slr, sh);
	signal f : state;
	signal p : state := idle;
	signal clk : STD_LOGIC;
	
	component selectable_clock
	Port ( clk : in std_logic;
	       s0 : in std_logic;
	       s1 : in std_logic;
	       out_clk : out std_logic);
	end component;

begin

	clk_0 : selectable_clock
	port map(
		clk => clk_in,
		s0 => '0',
		s1 => '1',
		out_clk => clk
	);

process (clk)
begin
	
	if rising_edge(clk) then
		p <= f;
	end if;
end process;

process (p, r, l)
begin
	case p is
		when idle =>
			if r='0' and l='0' then
				f <= idle;
			elsif r='0' and l='1' then	
				f <= sl;
			elsif r='1' and l='0' then
				f <= sr;
			else
				f <= slr;
			end if;
		when sl =>
			f <= idle;
		when sr =>
			f <= idle;
		when slr =>
			f <= sh;
		when sh =>
			f <= idle;
	end case;
end process;

process (p)
begin
	case p is
		when idle =>
			ro <= '0';
			lo <= '0';
			ho <= '0';
		when sl =>
			ro <= '0';
			lo <= '1';
			ho <= '0';
		when sr =>
			ro <= '1';
			lo <= '0';
			ho <= '0';
		when slr =>
			ro <= '1';
			lo <= '1';
			ho <= '0';
		when sh =>
			ro <= '0';
			lo <= '0';
			ho <= '1';
	end case;
end process;

end Behavioral;