LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY fsm_test IS
END fsm_test;
 
ARCHITECTURE behavior OF fsm_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT FSM
    PORT(
         li : IN  std_logic;
         ri : IN  std_logic;
         ro : OUT  std_logic;
         lo : OUT  std_logic;
         ho : OUT  std_logic;
         clk_in : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal li : std_logic := '0';
   signal ri : std_logic := '0';
   signal clk_in : std_logic := '0';

 	--Outputs
   signal ro : std_logic;
   signal lo : std_logic;
   signal ho : std_logic;

   -- Clock period definitions
   constant clk_in_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: FSM PORT MAP (
          li => li,
          ri => ri,
          ro => ro,
          lo => lo,
          ho => ho,
          clk_in => clk_in
        );

   -- Clock process definitions
   clk_in_process :process
   begin
		clk_in <= '0';
		wait for clk_in_period/2;
		clk_in <= '1';
		wait for clk_in_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_in_period*10;
		
		

      -- insert stimulus here 

      wait;
   end process;

END;