LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY shifter_test IS
	END shifter_test;

ARCHITECTURE behavior OF shifter_test IS 

    -- Component Declaration for the Unit Under Test (UUT)

	COMPONENT Shifter
		PORT(
			    i : IN  std_logic_vector(7 downto 0);
			    os : OUT  std_logic_vector(7 downto 0);
			    sh : IN  std_logic_vector(2 downto 0);
			    d : IN  std_logic
		    );
	END COMPONENT;


   --Inputs
	signal i : std_logic_vector(7 downto 0) := (others => '0');
	signal sh : std_logic_vector(2 downto 0) := (others => '0');
	signal d : std_logic := '0';

   --Outputs
	signal os : std_logic_vector(7 downto 0);

BEGIN

   -- Instantiate the Unit Under Test (UUT)
	uut: Shifter PORT MAP (
				      i => i,
				      os => os,
				      sh => sh,
				      d => d
			      );


   -- Stimulus process
	stim_proc: process
	begin		
      -- hold reset state for 100 ns.
		wait for 10 ns;

		d <= '1';
		sh <= "111";
		i <= "11111111";

		wait for 10 ns;

		sh <= "110";

		wait for 10 ns;

		sh <= "101";

		wait for 10 ns;

		sh <= "011";

		wait for 10 ns;

		sh <= "111";
		i <= "01111111";
		d <= '0';

		wait for 10 ns;

		sh <= "110";

		wait for 10 ns;

		sh <= "101";

		wait for 10 ns;

		sh <= "011";


		wait;
	end process;

END;