LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY mux_test IS
	END mux_test;

ARCHITECTURE behavior OF mux_test IS 

    -- Component Declaration for the Unit Under Test (UUT)

	COMPONENT Mux
		PORT(
			    A : IN  std_logic;
			    B : IN  std_logic;
			    S : IN  std_logic;
			    O : OUT  std_logic
		    );
	END COMPONENT;


   --Inputs
	signal A : std_logic := '0';
	signal B : std_logic := '0';
	signal S : std_logic := '0';

   --Outputs
	signal O : std_logic;

BEGIN

   -- Instantiate the Unit Under Test (UUT)
	uut: Mux PORT MAP (
				  A => A,
				  B => B,
				  S => S,
				  O => O
			  );

   -- Stimulus process
	stim_proc: process
	begin		
      -- hold reset state for 100 ns.
		wait for 100 ns;	

		A <= '1';

		wait for 100 ns;	

		S <= '1';

		wait for 100 ns;	

		B <= '1';

		wait for 100 ns;	

		A <= '0';

		wait for 100 ns;	

		A <= '1';
		B <= '0';

		wait for 100 ns;	

		S <= '0';

      -- insert stimulus here 

		wait;
	end process;

END;