shifter_test Project Status (09/23/2014 - 20:31:35)
Project File:	Barrel_Shifter_better.xise	Parser Errors:	No Errors
Module Name:	Shifter	Implementation State:	Programming File Generated
Target Device:	xc3s500e-4fg320	Errors:	No Errors
Product Version:	ISE 14.6	Warnings:	1 Warning (1 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of 4 input LUTs	44	9,312	1%
Number of occupied Slices	23	4,656	1%
Number of Slices containing only related logic	23	23	100%
Number of Slices containing unrelated logic	0	23	0%
Total Number of 4 input LUTs	45	9,312	1%
Number used as logic	44
Number used as a route-thru	1
Number of bonded IOBs	20	232	8%
Average Fanout of Non-Clock Nets	3.52

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue Sep 23 20:19:46 2014	0	1 Warning (1 new)	0
Translation Report	Current	Tue Sep 23 20:30:56 2014	0	0	0
Map Report	Current	Tue Sep 23 20:31:04 2014	0	0	2 Infos (0 new)
Place and Route Report	Current	Tue Sep 23 20:31:14 2014	0	0	1 Info (0 new)
Power Report
Post-PAR Static Timing Report	Current	Tue Sep 23 20:31:18 2014	0	0	0
Bitgen Report	Current	Tue Sep 23 20:31:26 2014	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Out of Date	Tue Sep 23 20:18:58 2014
WebTalk Report	Current	Tue Sep 23 20:31:28 2014
WebTalk Log File	Current	Tue Sep 23 20:31:34 2014

Date Generated: 09/23/2014 - 20:31:36