-------------------------------------------------------------------------------- Release 14.6 Trace (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml Shifter.twx Shifter.ncd -o Shifter.twr Shifter.pcf -ucf Shifter.ucf Design file: Shifter.ncd Physical constraint file: Shifter.pcf Device,package,speed: xc3s500e,fg320,-4 (PRODUCTION 1.27 2013-06-08) Report level: verbose report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:2698 - No timing constraints found, doing default enumeration. INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation. INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Pad to Pad ---------------+---------------+---------+ Source Pad |Destination Pad| Delay | ---------------+---------------+---------+ d |os<0> | 10.248| d |os<1> | 13.258| d |os<2> | 10.236| d |os<3> | 11.453| d |os<4> | 10.652| d |os<5> | 10.080| d |os<6> | 10.835| d |os<7> | 11.196| i<0> |os<0> | 9.896| i<0> |os<1> | 11.097| i<0> |os<2> | 9.458| i<0> |os<3> | 11.702| i<0> |os<4> | 10.059| i<0> |os<5> | 10.632| i<0> |os<6> | 10.438| i<0> |os<7> | 10.869| i<1> |os<0> | 11.004| i<1> |os<1> | 10.243| i<1> |os<2> | 10.273| i<1> |os<3> | 11.621| i<1> |os<4> | 9.811| i<1> |os<5> | 10.551| i<1> |os<6> | 11.253| i<1> |os<7> | 10.788| i<2> |os<0> | 12.470| i<2> |os<1> | 11.678| i<2> |os<2> | 11.399| i<2> |os<3> | 11.184| i<2> |os<4> | 10.354| i<2> |os<5> | 10.216| i<2> |os<6> | 11.796| i<2> |os<7> | 10.694| i<3> |os<0> | 12.288| i<3> |os<1> | 10.767| i<3> |os<2> | 11.217| i<3> |os<3> | 11.156| i<3> |os<4> | 10.190| i<3> |os<5> | 10.188| i<3> |os<6> | 10.295| i<3> |os<7> | 10.666| i<4> |os<0> | 13.135| i<4> |os<1> | 11.375| i<4> |os<2> | 11.845| i<4> |os<3> | 11.157| i<4> |os<4> | 10.905| i<4> |os<5> | 10.300| i<4> |os<6> | 10.016| i<4> |os<7> | 10.707| i<5> |os<0> | 12.141| i<5> |os<1> | 10.967| i<5> |os<2> | 10.860| i<5> |os<3> | 10.341| i<5> |os<4> | 9.911| i<5> |os<5> | 10.414| i<5> |os<6> | 9.737| i<5> |os<7> | 10.821| i<6> |os<0> | 13.217| i<6> |os<1> | 10.916| i<6> |os<2> | 9.555| i<6> |os<3> | 10.290| i<6> |os<4> | 10.987| i<6> |os<5> | 9.572| i<6> |os<6> | 10.482| i<6> |os<7> | 10.165| i<7> |os<0> | 12.594| i<7> |os<1> | 10.081| i<7> |os<2> | 9.495| i<7> |os<3> | 10.232| i<7> |os<4> | 10.364| i<7> |os<5> | 8.443| i<7> |os<6> | 10.282| i<7> |os<7> | 10.080| sh<0> |os<0> | 14.356| sh<0> |os<1> | 12.326| sh<0> |os<2> | 13.111| sh<0> |os<3> | 13.553| sh<0> |os<4> | 12.126| sh<0> |os<5> | 12.483| sh<0> |os<6> | 13.065| sh<0> |os<7> | 12.720| sh<1> |os<0> | 14.120| sh<1> |os<1> | 13.119| sh<1> |os<2> | 11.343| sh<1> |os<3> | 11.836| sh<1> |os<4> | 11.890| sh<1> |os<5> | 11.234| sh<1> |os<6> | 11.876| sh<1> |os<7> | 12.135| sh<2> |os<0> | 12.280| sh<2> |os<1> | 12.362| sh<2> |os<2> | 10.356| sh<2> |os<3> | 10.100| sh<2> |os<4> | 11.326| sh<2> |os<5> | 10.984| sh<2> |os<6> | 9.639| sh<2> |os<7> | 11.579| ---------------+---------------+---------+ Analysis completed Tue Sep 23 20:31:17 2014 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 162 MB