LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
 
ENTITY small_adder IS
END small_adder;
 
ARCHITECTURE behavior OF small_adder IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT adder_block
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         ci : IN  std_logic;
         s : OUT  std_logic;
         co : OUT  std_logic;
         op_sel : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';
   signal ci : std_logic := '0';
   signal op_sel : std_logic := '0';

 	--Outputs
   signal s : std_logic;
   signal co : std_logic;
   
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: adder_block PORT MAP (
          a => a,
          b => b,
          ci => ci,
          s => s,
          co => co,
          op_sel => op_sel
        );

   
   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 10 ns;

		a <= '1';
		
		wait for 10 ns;
		
		a <= '0';
		b <= '1';
		
		wait for 10 ns;
		
		a <= '1';
		
		wait for 10 ns;
		
		a <= '0';
		b <= '0';
		
		wait for 10 ns;
		
		op_sel <= '1';
		ci <= '1';
		
		wait for 10 ns;

		a <= '1';
		
		wait for 10 ns;
		
		a <= '0';
		b <= '1';
		
		wait for 10 ns;
		
		a <= '1';

      wait;
   end process;

END;