-- Selectable output frequency clock divider code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity selectable_clock is
	Port ( clk : in std_logic;
	       s0 : in std_logic;
	       s1 : in std_logic;
	       out_clk : out std_logic);
end selectable_clock;
--If s1 and s0 are both low, the output clock rate is 1/10 Hz.
--If s1 is low and s0 is high, the output clock rate is 1 Hz.
--If s1 is high and s0 is low, the output clock rate is 10 Hz.
--If s1 and s0 are both high, the output clock rate is 1 KHz.
architecture Behavioral of selectable_clock is
begin
	process (clk, s0, s1)
		variable count : integer := 0;
	begin
		if clk = '1' and clk'event then
			count := count + 1;
			-- Start a process.
			-- Variable declaration.
			-- Rising edge detection.
			-- Code to create the 1/10 Hz clock.
			if s0 = '0' and s1 = '0' then
				if count >= 500000000 then
					-- Taken off a 50MHz clock.
					count := 0;
				-- Reset count for next cycle.
				end if;
				if count >= 0 and count <= 250000000 then
					out_clk <= '1';
				-- High portion of 1/10 HZ clock.
				else
					out_clk <= '0';
				-- Low portion of 1/10 HZ clock.
				end if;
			end if;
			-- Code to create the 1 Hz clock.
			if s0 = '1' and s1 = '0' then
				if count >= 50000000 then
					-- Taken off a 50MHz clock.
					count := 0;
				-- Reset count for next cycle.
				end if;
				if count >= 0 and count <= 25000000 then
					out_clk <= '1';
				-- High portion of 1 HZ clock.
				else
					out_clk <= '0';
				-- Low portion of 1 HZ clock.
				end if;
			end if;
			-- Code to create the 10 Hz clock.
			if s0 = '0' and s1 = '1' then
				if count >= 5000000 then
					-- Taken off a 50MHz clock.
					count := 0;
				-- Reset count for next cycle.
				end if;
				if count >= 0 and count <= 2500000 then
					out_clk <= '1';
				-- High portion of 10 HZ clock.
				else
					out_clk <= '0';
				-- Low portion of 10 HZ clock.
				end if;
			end if;
			-- Code to create the 1 KHz clock.
			if s0 = '1' and s1 = '1' then
				if count >= 50000 then
					-- Taken off a 50MHz clock.
					count := 0;
				-- Reset count for next cycle.
				end if;
				if count >= 0 and count <= 25000 then
					out_clk <= '1';
				-- High portion of 1 KHz clock.
				else
					out_clk <= '0';
				-- Low portion of 1 KHz clock.
				end if;
			end if;
		end if;
	end process;
end Behavioral;