sar_fsm Project Status (11/11/2014 - 21:12:33)
Project File: SAR.xise Parser Errors: No Errors
Module Name: sar_fsm Implementation State: Programming File Generated
Target Device: xc3s500e-4fg320
  • Errors:
No Errors
Product Version:ISE 14.6
  • Warnings:
17 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 41 9,312 1%  
Number of 4 input LUTs 74 9,312 1%  
Number of occupied Slices 62 4,656 1%  
    Number of Slices containing only related logic 62 62 100%  
    Number of Slices containing unrelated logic 0 62 0%  
Total Number of 4 input LUTs 107 9,312 1%  
    Number used as logic 74      
    Number used as a route-thru 33      
Number of bonded IOBs 12 232 5%  
    IOB Latches 9      
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.30      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Nov 11 21:11:52 201405 Warnings (0 new)5 Infos (0 new)
Translation ReportCurrentTue Nov 11 21:11:58 2014000
Map ReportCurrentTue Nov 11 21:12:03 201405 Warnings (0 new)2 Infos (0 new)
Place and Route ReportCurrentTue Nov 11 21:12:15 201403 Warnings (0 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentTue Nov 11 21:12:19 2014006 Infos (0 new)
Bitgen ReportCurrentTue Nov 11 21:12:25 201404 Warnings (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentTue Nov 11 21:12:26 2014
WebTalk Log FileCurrentTue Nov 11 21:12:32 2014

Date Generated: 11/11/2014 - 21:12:33