Release 14.6 Map P.68d (nt64) Xilinx Map Application Log File for Design 'sar_fsm' Design Information ------------------ Command Line : map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o sar_fsm_map.ncd sar_fsm.ngd sar_fsm.pcf Target Device : xc3s500e Target Package : fg320 Target Speed : -4 Mapper Version : spartan3e -- $Revision: 1.55 $ Mapped Date : Tue Nov 11 21:12:00 2014 vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:54 - 'xc3s500e' is a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- Mapping design into LUTs... Running directed packing... WARNING:Pack:1543 - The register done_out has the property IOB=TRUE, but was not packed into the input side of an I/O component. The register symbol "done_out" has no connections inside the I/O component. Running delay-based LUT packing... Running related packing... Updating timing models... WARNING:PhysDesignRules:372 - Gated clock. Clock net count_0_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net count_1_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net count_2_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:PhysDesignRules:372 - Gated clock. Clock net count_3_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Design Summary -------------- Design Summary: Number of errors: 0 Number of warnings: 5 Logic Utilization: Number of Slice Flip Flops: 41 out of 9,312 1% Number of 4 input LUTs: 74 out of 9,312 1% Logic Distribution: Number of occupied Slices: 62 out of 4,656 1% Number of Slices containing only related logic: 62 out of 62 100% Number of Slices containing unrelated logic: 0 out of 62 0% *See NOTES below for an explanation of the effects of unrelated logic. Total Number of 4 input LUTs: 107 out of 9,312 1% Number used as logic: 74 Number used as a route-thru: 33 The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. Number of bonded IOBs: 12 out of 232 5% IOB Latches: 9 Number of BUFGMUXs: 1 out of 24 4% Average Fanout of Non-Clock Nets: 2.30 Peak Memory Usage: 276 MB Total REAL time to MAP completion: 2 secs Total CPU time to MAP completion: 1 secs NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "sar_fsm_map.mrp" for details.