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Release 14.6 Trace  (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4
-n 3 -fastpaths -xml sar_fsm.twx sar_fsm.ncd -o sar_fsm.twr sar_fsm.pcf -ucf
sar_fsm.ucf

Design file:              sar_fsm.ncd
Physical constraint file: sar_fsm.pcf
Device,package,speed:     xc3s500e,fg320,-4 (PRODUCTION 1.27 2013-06-08)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock en to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
dac_out<0>  |    8.278(F)|count_0_not0001   |   0.000|
dac_out<1>  |    8.343(F)|count_1_not0001   |   0.000|
dac_out<2>  |    8.378(F)|count_2_not0001   |   0.000|
dac_out<3>  |    7.573(F)|count_3_not0001   |   0.000|
result<0>   |    8.463(F)|count_0_not0001   |   0.000|
result<1>   |    8.887(F)|count_1_not0001   |   0.000|
result<2>   |    8.130(F)|count_2_not0001   |   0.000|
result<3>   |    7.673(F)|count_3_not0001   |   0.000|
------------+------------+------------------+--------+

Clock start to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
dac_out<0>  |   12.334(F)|count_0_not0001   |   0.000|
dac_out<1>  |   12.321(F)|count_1_not0001   |   0.000|
dac_out<2>  |   10.891(F)|count_2_not0001   |   0.000|
dac_out<3>  |   10.490(F)|count_3_not0001   |   0.000|
result<0>   |   12.519(F)|count_0_not0001   |   0.000|
result<1>   |   12.865(F)|count_1_not0001   |   0.000|
result<2>   |   10.643(F)|count_2_not0001   |   0.000|
result<3>   |   10.590(F)|count_3_not0001   |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk_in
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_in         |   13.362|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock en
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
start          |         |         |    4.025|    4.025|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock start
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
start          |         |         |    1.987|    1.987|
---------------+---------+---------+---------+---------+


Analysis completed Tue Nov 11 21:12:19 2014 
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Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 168 MB