propgen Project Status (09/30/2014 - 21:00:01)
Project File: HighSpeedAdder.xise Parser Errors: No Errors
Module Name: propgen Implementation State: Programming File Not Generated
Target Device: xc3s500e-4fg320
  • Errors:
 
Product Version:ISE 14.6
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateTue Sep 30 20:58:25 2014
WebTalk ReportCurrentTue Sep 30 20:59:54 2014
WebTalk Log FileCurrentTue Sep 30 21:00:01 2014

Date Generated: 09/30/2014 - 21:00:01