LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY claadder_test IS
	END claadder_test;

ARCHITECTURE behavior OF claadder_test IS 

    -- Component Declaration for the Unit Under Test (UUT)

	COMPONENT claadder
		PORT(
			    cin : IN  std_logic;
			    co : OUT  std_logic;
			    A : IN  std_logic_vector(3 downto 0);
			    B : IN  std_logic_vector(3 downto 0);
			    S : OUT  std_logic_vector(3 downto 0)
		    );
	END COMPONENT;


   --Inputs
	signal cin : std_logic := '0';
	signal A : std_logic_vector(3 downto 0) := (others => '0');
	signal B : std_logic_vector(3 downto 0) := (others => '0');

   --Outputs
	signal co : std_logic;
	signal S : std_logic_vector(3 downto 0);

BEGIN

   -- Instantiate the Unit Under Test (UUT)
	uut: claadder PORT MAP (
				       cin => cin,
				       co => co,
				       A => A,
				       B => B,
				       S => S
			       );

   -- Stimulus process
	stim_proc: process
	begin		
      -- hold reset state for 100 ns.
		wait for 10 ns;	

		A <= "0001";

		wait for 10 ns;	

		B <= "0001";

		wait for 10 ns;	

		A <= "0010";

		wait for 10 ns;	

		A <= "1111";

		wait for 10 ns;	

		A <= "0111";
		cin <= '1';

		wait for 10 ns;	

		B <= "0111";

		wait for 10 ns;	

		B <= "0000";
		A <= "0000";

		wait;
	end process;

END;