propgen Project Status (09/30/2014 - 21:00:01)
Project File: HighSpeedAdder.xise Parser Errors: No Errors
Module Name: claadder Implementation State: Programming File Generated
Target Device: xc3s500e-4fg320
  • Errors:
 No Errors
Product Version:ISE 14.6
  • Warnings:
 1 Warning (0 new)
Design Goal: Balanced
  • Routing Results:
 All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
 0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 8 9,312 1%  
Number of occupied Slices 5 4,656 1%  
    Number of Slices containing only related logic 5 5 100%  
    Number of Slices containing unrelated logic 0 5 0%  
Total Number of 4 input LUTs 8 9,312 1%  
Number of bonded IOBs 14 232 6%  
Average Fanout of Non-Clock Nets 2.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Sep 30 20:59:24 201401 Warning (0 new)0
Translation ReportCurrentTue Sep 30 20:59:30 2014000
Map ReportCurrentTue Sep 30 20:59:35 2014002 Infos (0 new)
Place and Route ReportCurrentTue Sep 30 20:59:44 2014001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentTue Sep 30 20:59:48 2014006 Infos (0 new)
Bitgen ReportCurrentTue Sep 30 20:59:54 2014000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateTue Sep 30 20:58:25 2014
WebTalk ReportCurrentTue Sep 30 20:59:54 2014
WebTalk Log FileCurrentTue Sep 30 21:00:01 2014

Date Generated: 09/30/2014 - 21:00:01