LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
 
ENTITY Counter_test IS
END Counter_test;
 
ARCHITECTURE behavior OF Counter_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Counter
    PORT(
         clk_in : IN  std_logic;
         o : OUT  std_logic_vector(3 downto 0);
         tc : OUT  std_logic;
         reset : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk_in : std_logic := '0';
   signal reset : std_logic := '0';

 	--Outputs
   signal o : std_logic_vector(3 downto 0);
   signal tc : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Counter PORT MAP (
          clk_in => clk_in,
          o => o,
          tc => tc,
          reset => reset
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk_in <= '0';
		wait for clk_period/2;
		clk_in <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;