Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.6 (ISE) - P.68d Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s500e
Project ID (random number) 82f0d94137d34679837fecd9ed93309e.0E70EDCEE72445CF9C7222E428D12CF7.5 Target Package: fg320
Registration ID 174534306_174123213_210564973_342 Target Speed: -4
Date Generated 2014-08-26T20:37:45 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Xors=1
  • 1-bit xor2=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=9
  • AGG_IO=9
  • AGG_SLICE=3
  • NUM_4_INPUT_LUT=5
  • NUM_BONDED_IBUF=5
  • NUM_BONDED_IOB=4
  • NUM_SLICEL=3
 		NetStatistics
  • NumNets_Active=17
  • NumNodesOfType_Active_DOUBLE=32
  • NumNodesOfType_Active_DUMMY=18
  • NumNodesOfType_Active_DUMMYESC=5
  • NumNodesOfType_Active_HUNIHEX=7
  • NumNodesOfType_Active_INPUT=24
  • NumNodesOfType_Active_IOBOUTPUT=5
  • NumNodesOfType_Active_OUTPUT=3
  • NumNodesOfType_Active_PREBXBY=6
  • NumNodesOfType_Active_VFULLHEX=8
  • NumNodesOfType_Active_VUNIHEX=14
 SiteStatistics
  • IOB-DIFFM=2
  • IOB-DIFFS=2
  • SLICEL-SLICEM=2
 		SiteSummary
  • IBUF=5
  • IBUF_INBUF=5
  • IBUF_PAD=5
  • IOB=4
  • IOB_OUTBUF=4
  • IOB_PAD=4
  • SLICEL=3
  • SLICEL_F=2
  • SLICEL_F5MUX=2
  • SLICEL_G=3
 
Configuration Data
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:5]
 IOB
  • O1=[O1_INV:1] [O1:3]
 IOB_OUTBUF
  • IN=[IN_INV:1] [IN:3]
 IOB_PAD
  • DRIVEATTRBOX=[12:4]
  • IOATTRBOX=[LVCMOS25:4]
  • SLEW=[SLOW:4]
 SLICEL
  • BX=[BX_INV:0] [BX:2]
 SLICEL_F5MUX
  • S0=[S0:2] [S0_INV:0]
 
Pin Data
IBUF
  • I=5
  • PAD=5
 IBUF_INBUF
  • IN=5
  • OUT=5
 IBUF_PAD
  • PAD=5
 IOB
  • O1=4
  • PAD=4
 IOB_OUTBUF
  • IN=4
  • OUT=4
 IOB_PAD
  • PAD=4
 SLICEL
  • BX=2
  • F1=2
  • F2=2
  • F3=2
  • F4=2
  • G1=3
  • G2=3
  • G3=3
  • G4=1
  • X=2
  • Y=1
 SLICEL_F
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • D=2
 SLICEL_F5MUX
  • F=2
  • G=2
  • OUT=2
  • S0=2
 SLICEL_G
  • A1=3
  • A2=3
  • A3=3
  • A4=1
  • D=3
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 80 55 0 0 0 0 0
bitgen 111 111 0 0 0 0 0
libgen 1 1 0 0 0 0 0
map 147 138 0 0 0 0 0
ngc2edif 37 37 0 0 0 0 0
ngcbuild 3 3 0 0 0 0 0
ngdbuild 157 157 0 0 0 0 0
par 138 122 16 0 0 0 0
platgen 3 3 0 0 0 0 0
psf2Edward 2 2 0 0 0 0 0
trce 121 121 0 0 0 0 0
xdsgen 2 2 0 0 0 0 0
xps 3 3 0 0 0 0 0
xst 297 289 0 0 0 0 0
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2014-08-26T19:00:29 PROP_intWbtProjectID=0E70EDCEE72445CF9C7222E428D12CF7
PROP_intWbtProjectIteration=5 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s500e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=fg320
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=5 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT3=2 NGDBUILD_NUM_LUT4=3
NGDBUILD_NUM_MUXF5=2 NGDBUILD_NUM_OBUF=4
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=5 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT3=2 NGDBUILD_NUM_LUT4=3
NGDBUILD_NUM_MUXF5=2 NGDBUILD_NUM_OBUF=4
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s500e-4-fg320 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5