| BCD_to_Excess3 Project Status (08/26/2014 - 20:37:53) | |||
| Project File: | BCD_Converter.xise | Parser Errors: | |
| Module Name: | BCD_to_Excess3 | Implementation State: | Programming File Generated |
| Target Device: | xc3s500e-4fg320 |
|
No Errors |
| Product Version: | ISE 14.6 |
|
1 Warning (1 new) |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
|
|
| Environment: | System Settings |
|
0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of 4 input LUTs | 5 | 9,312 | 1% | ||
| Number of occupied Slices | 3 | 4,656 | 1% | ||
| Number of Slices containing only related logic | 3 | 3 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 3 | 0% | ||
| Total Number of 4 input LUTs | 5 | 9,312 | 1% | ||
| Number of bonded IOBs | 9 | 232 | 3% | ||
| Average Fanout of Non-Clock Nets | 3.00 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | ||||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Tue Aug 26 20:37:12 2014 | 0 | 1 Warning (1 new) | 0 | |
| Translation Report | Current | Tue Aug 26 20:37:18 2014 | 0 | 0 | 0 | |
| Map Report | Current | Tue Aug 26 20:37:24 2014 | 0 | 0 | 2 Infos (2 new) | |
| Place and Route Report | Current | Tue Aug 26 20:37:36 2014 | 0 | 0 | 1 Info (1 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Tue Aug 26 20:37:40 2014 | 0 | 0 | 6 Infos (6 new) | |
| Bitgen Report | Current | Tue Aug 26 20:37:46 2014 | 0 | 0 | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Report | Current | Tue Aug 26 20:37:48 2014 | |
| WebTalk Log File | Current | Tue Aug 26 20:37:54 2014 | |