Release 14.6 Map P.68d (nt64)
Xilinx Map Application Log File for Design 'BCD_to_Excess3'

Design Information
------------------
Command Line   : map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off
-c 100 -o BCD_to_Excess3_map.ncd BCD_to_Excess3.ngd BCD_to_Excess3.pcf 
Target Device  : xc3s500e
Target Package : fg320
Target Speed   : -4
Mapper Version : spartan3e -- $Revision: 1.55 $
Mapped Date    : Tue Aug 26 20:37:20 2014

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1417@ephesus.ece.iit.edu;1717@valkyrie.ece.iit.edu;27000@skew.ece.iit.edu'.
INFO:Security:54 - 'xc3s500e' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license
directory.
WARNING:Security:44 - Since no license file was found,
       please run the Xilinx License Configuration Manager
       (xlcm or "Manage Xilinx Licenses")
       to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of 4 input LUTs:                 5 out of   9,312    1%
Logic Distribution:
  Number of occupied Slices:              3 out of   4,656    1%
    Number of Slices containing only related logic:       3 out of       3 100%
    Number of Slices containing unrelated logic:          0 out of       3   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:           5 out of   9,312    1%
  Number of bonded IOBs:                  9 out of     232    3%

Average Fanout of Non-Clock Nets:                3.00

Peak Memory Usage:  274 MB
Total REAL time to MAP completion:  2 secs 
Total CPU time to MAP completion:   1 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "BCD_to_Excess3_map.mrp" for details.