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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:02:54 08/26/2014 
-- Design Name: 
-- Module Name:    BCD_to_Excess3 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BCD_to_Excess3 is
    Port ( input : in  STD_LOGIC_VECTOR (3 downto 0);
			  SEL : in STD_LOGIC;
           output : out  STD_LOGIC_VECTOR (3 downto 0));
end BCD_to_Excess3;

architecture Universal_Converter of BCD_to_Excess3 is
begin

process(SEL)
begin
	if SEL='0' then
		output(0) <= not input(0);
		output(1) <= input(1) xnor input(0);
		output(2) <= (input(2) and (not input(1)) and (not input(0))) or ((not input(2)) and (input(1) or input(0)));
		output(3) <= input(3) or ( input(0) and input(2) ) or (input(1) and input(2) );
	else
		output(0) <= not input(0);
		output(1) <= (input(1) and (not input(0))) or (input(0) and (not input(1)));
		output(2) <= ((not input(2)) and (not input(1))) or (input(1) and ((input(2) and input(0)) or (input(3) and (not input(0)))));
		output(3) <= (input(3) and input(2)) or (input(3) and input(1) and input(0));
	end if;
end process;
end Universal_Converter;