Release 14.6 par P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

GUEST1-PC::  Tue Aug 26 20:37:26 2014

par -w -intstyle ise -ol high -t 1 BCD_to_Excess3_map.ncd BCD_to_Excess3.ncd
BCD_to_Excess3.pcf 


Constraints file: BCD_to_Excess3.pcf.
Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx\14.6\ISE_DS\ISE\.
   "BCD_to_Excess3" is an NCD, version 3.2, device xc3s500e, package fg320, speed -4
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'1417@ephesus.ece.iit.edu;1717@valkyrie.ece.iit.edu;27000@skew.ece.iit.edu'.
INFO:Security:54 - 'xc3s500e' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license directory.
WARNING:Security:44 - Since no license file was found,
       please run the Xilinx License Configuration Manager
       (xlcm or "Manage Xilinx Licenses")
       to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.

----------------------------------------------------------------------

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.27 2013-06-08".


Design Summary Report:

 Number of External IOBs                           9 out of 232     3%

   Number of External Input IOBs                  5

      Number of External Input IBUFs              5
        Number of LOCed External Input IBUFs      5 out of 5     100%


   Number of External Output IOBs                 4

      Number of External Output IOBs              4
        Number of LOCed External Output IOBs      4 out of 4     100%


   Number of External Bidir IOBs                  0


   Number of Slices                          3 out of 4656    1%
      Number of SLICEMs                      0 out of 2328    0%



Overall effort level (-ol):   High 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 2 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Starting Placer
Total REAL time at the beginning of Placer: 2 secs 
Total CPU  time at the beginning of Placer: 1 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:7bcd4a21) REAL time: 2 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:7bcd4a21) REAL time: 2 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:7bcd4a21) REAL time: 2 secs 

Phase 4.2  Initial Clock and IO Placement
Phase 4.2  Initial Clock and IO Placement (Checksum:7bcd4a21) REAL time: 2 secs 

Phase 5.30  Global Clock Region Assignment
Phase 5.30  Global Clock Region Assignment (Checksum:7bcd4a21) REAL time: 2 secs 

Phase 6.36  Local Placement Optimization
Phase 6.36  Local Placement Optimization (Checksum:7bcd4a21) REAL time: 2 secs 

Phase 7.8  Global Placement
....
Phase 7.8  Global Placement (Checksum:d675c8b6) REAL time: 2 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:d675c8b6) REAL time: 2 secs 

Phase 9.18  Placement Optimization
Phase 9.18  Placement Optimization (Checksum:d5189e94) REAL time: 2 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:d5189e94) REAL time: 2 secs 

Total REAL time to Placer completion: 2 secs 
Total CPU  time to Placer completion: 1 secs 
Writing design to file BCD_to_Excess3.ncd



Starting Router


Phase  1  : 24 unrouted;      REAL time: 6 secs 

Phase  2  : 24 unrouted;      REAL time: 6 secs 

Phase  3  : 4 unrouted;      REAL time: 6 secs 

Phase  4  : 4 unrouted; (Par is working to improve performance)     REAL time: 6 secs 

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 6 secs 

Updating file: BCD_to_Excess3.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 6 secs 

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 6 secs 

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 6 secs 

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 6 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 5 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

Timing Score: 0 (Setup: 0, Hold: 0)



Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  275 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file BCD_to_Excess3.ncd



PAR done!