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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:06:45 11/11/2014 
-- Design Name: 
-- Module Name:    debounce - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity debounce is
	Port ( input : in std_logic;
		clk_in : in std_logic;
		output : out std_logic);
end debounce;

architecture Behavioral of debounce is
begin
	process (clk_in, input) -- Start a process.
	variable count : integer := 0; -- Variable declaration.
	begin
		if clk_in = '1' and clk_in'event then -- Rising edge detection.
			if input = '1' then -- Input is high at clock.
				count := count + 1; -- Increment count.
			else -- Input is low at clock.
				count := 0; -- Reset count.
			end if;
		
			if count > 1000000 then -- Input high long enough to
										-- output.
				output <= '1'; -- Output high.
			else -- Input not high long enough.
				output <= '0'; -- Output low.
			end if;
		end if;
	end process;
end Behavioral;