adc Project Status (11/11/2014 - 19:16:44)
Project File:	ADC.xise	Parser Errors:	No Errors
Module Name:	adc	Implementation State:	Synthesized (Failed)
Target Device:	xc3s500e-4fg320	Errors:	X 1 Error (1 new)
Product Version:	ISE 14.6	Warnings:	No Warnings
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue Nov 11 19:16:42 2014	X 1 Error (1 new)	0	0
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 11/11/2014 - 19:17:56