Counter Project Status (11/04/2014 - 21:00:26)
Project File:	ADC.xise	Parser Errors:	X 1 Error
Module Name:	Counter	Implementation State:	Synthesized (Failed)
Target Device:	xc3s500e-4fg320	Errors:
Product Version:	ISE 14.6	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
CPLD Fitter Report (Text)
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 11/04/2014 - 21:06:12