Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.6 (ISE) - P.68d Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s500e
Project ID (random number) c2e23f69b7254c0da99aca94e4457c97.2944C65F69701706D045F2C5AFDB20AF.37 Target Package: fg320
Registration ID 174534306_174123213_210591200_969 Target Speed: -4
Date Generated 2014-12-02T20:33:57 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=2
  • 32-bit adder=2
 Comparators=24
  • 32-bit comparator greatequal=16
  • 32-bit comparator lessequal=8
 Counters=1
  • 4-bit up counter=1
 FSMs=2 Latches=11
  • 1-bit latch=9
  • 8-bit latch=2
 Registers=158
  • Flip-Flops=158
 		MiscellaneousStatistics
  • AGG_BONDED_IO=30
  • AGG_IO=30
  • AGG_SLICE=186
  • NUM_4_INPUT_LUT=343
  • NUM_BONDED_IBUF=11
  • NUM_BONDED_IOB=19
  • NUM_BUFGMUX=1
  • NUM_CYMUX=122
  • NUM_DP_RAM=16
  • NUM_IOB_LATCH=8
  • NUM_LUT_RT=37
  • NUM_MULTAND=2
  • NUM_RAM32=52
  • NUM_RAMB16=1
  • NUM_SLICEL=152
  • NUM_SLICEM=34
  • NUM_SLICE_FF=129
  • NUM_XOR=69
 		NetStatistics
  • NumNets_Active=422
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=10
  • NumNodesOfType_Active_BRAMDUMMY=18
  • NumNodesOfType_Active_CLKPIN=107
  • NumNodesOfType_Active_CNTRLPIN=84
  • NumNodesOfType_Active_DOUBLE=898
  • NumNodesOfType_Active_DUMMY=1067
  • NumNodesOfType_Active_DUMMYBANK=12
  • NumNodesOfType_Active_DUMMYESC=7
  • NumNodesOfType_Active_GLOBAL=36
  • NumNodesOfType_Active_HFULLHEX=11
  • NumNodesOfType_Active_HLONG=2
  • NumNodesOfType_Active_HUNIHEX=44
  • NumNodesOfType_Active_INPUT=1275
  • NumNodesOfType_Active_IOBOUTPUT=15
  • NumNodesOfType_Active_OMUX=311
  • NumNodesOfType_Active_OUTPUT=360
  • NumNodesOfType_Active_PREBXBY=341
  • NumNodesOfType_Active_VFULLHEX=54
  • NumNodesOfType_Active_VLONG=10
  • NumNodesOfType_Active_VUNIHEX=92
  • NumNodesOfType_Vcc_BRAMDUMMY=1
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=11
  • NumNodesOfType_Vcc_PREBXBY=7
  • NumNodesOfType_Vcc_VCCOUT=11
 SiteStatistics
  • IBUF-DIFFM=4
  • IBUF-DIFFS=3
  • IOB-DIFFM=10
  • IOB-DIFFS=9
  • SLICEL-SLICEM=44
 		SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=11
  • IBUF_IFD_DELAY=8
  • IBUF_IFF1=8
  • IBUF_INBUF=11
  • IBUF_PAD=11
  • IOB=19
  • IOB_INBUF=4
  • IOB_OUTBUF=19
  • IOB_PAD=19
  • RAMB16=1
  • RAMB16_RAMB16=1
  • RAMB16_RAMB16A=1
  • SLICEL=152
  • SLICEL_C1VDD=9
  • SLICEL_C2VDD=15
  • SLICEL_CYMUXF=66
  • SLICEL_CYMUXG=56
  • SLICEL_F=139
  • SLICEL_F5MUX=10
  • SLICEL_FAND=1
  • SLICEL_FFX=51
  • SLICEL_FFY=52
  • SLICEL_G=136
  • SLICEL_GAND=1
  • SLICEL_GNDF=48
  • SLICEL_GNDG=33
  • SLICEL_XORF=33
  • SLICEL_XORG=36
  • SLICEM=34
  • SLICEM_BYINVOUTUSED=8
  • SLICEM_BYOUTUSED=8
  • SLICEM_DIGUSED=8
  • SLICEM_F=34
  • SLICEM_F5MUX=26
  • SLICEM_F6MUX=8
  • SLICEM_FFX=10
  • SLICEM_FFY=16
  • SLICEM_G=34
  • SLICEM_WSGEN=34
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
 IBUF
  • ICLK1=[ICLK1_INV:8] [ICLK1:0]
 IBUF_IFF1
  • CK=[CK:0] [CK_INV:8]
  • IFF1_INIT_ATTR=[INIT0:8]
  • LATCH_OR_FF=[LATCH:8]
 IBUF_INBUF
  • IFD_DELAY_VALUE=[DLY3:8]
 IBUF_PAD
  • IOATTRBOX=[LVTTL:1] [LVCMOS25:10]
 IOB
  • O1=[O1_INV:0] [O1:19]
  • T1=[T1_INV:0] [T1:4]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:19]
  • TRI=[TRI_INV:0] [TRI:4]
 IOB_PAD
  • DRIVEATTRBOX=[2:10] [12:9]
  • IOATTRBOX=[LVTTL:19]
  • SLEW=[SLOW:19]
 RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • SSRA=[SSRA_INV:0] [SSRA:1]
  • WEA=[WEA:1] [WEA_INV:0]
 RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • PORTA_ATTR=[1024X18:1]
  • SSRA=[SSRA_INV:0] [SSRA:1]
  • WEA=[WEA:1] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:1]
 SLICEL
  • BX=[BX_INV:0] [BX:27]
  • BY=[BY:7] [BY_INV:1]
  • CE=[CE:3] [CE_INV:5]
  • CIN=[CIN_INV:0] [CIN:55]
  • CLK=[CLK:64] [CLK_INV:0]
  • SR=[SR:26] [SR_INV:4]
 SLICEL_CYMUXF
  • 0=[0:66] [0_INV:0]
  • 1=[1_INV:0] [1:66]
 SLICEL_CYMUXG
  • 0=[0:56] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:10] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:0] [CE_INV:5]
  • CK=[CK:51] [CK_INV:0]
  • D=[D:51] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:51]
  • FFX_SR_ATTR=[SRLOW:51]
  • LATCH_OR_FF=[FF:51]
  • SR=[SR:20] [SR_INV:4]
  • SYNC_ATTR=[ASYNC:27] [SYNC:24]
 SLICEL_FFY
  • CE=[CE:3] [CE_INV:5]
  • CK=[CK:52] [CK_INV:0]
  • D=[D:51] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:49] [INIT1:3]
  • FFY_SR_ATTR=[SRLOW:51] [SRHIGH:1]
  • LATCH_OR_FF=[FF:52]
  • SR=[SR:17] [SR_INV:4]
  • SYNC_ATTR=[ASYNC:29] [SYNC:23]
 SLICEL_XORF
  • 1=[1_INV:0] [1:33]
 SLICEM
  • ALTDIG=[ALTDIG:8] [ALTDIG_INV:0]
  • BX=[BX_INV:0] [BX:26]
  • BY=[BY:34] [BY_INV:0]
  • CE=[CE:8] [CE_INV:0]
  • CLK=[CLK:34] [CLK_INV:0]
  • SR=[SR:24] [SR_INV:10]
 SLICEM_BYINVOUTUSED
  • 0=[0:8] [0_INV:0]
 SLICEM_BYOUTUSED
  • 0=[0:8] [0_INV:0]
 SLICEM_DIGUSED
  • 0=[0:8] [0_INV:0]
 SLICEM_F
  • DI=[DI:34] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:8]
  • LUT_OR_MEM=[RAM:34]
 SLICEM_F5MUX
  • S0=[S0:26] [S0_INV:0]
 SLICEM_F6MUX
  • S0=[S0:8] [S0_INV:0]
 SLICEM_FFX
  • CK=[CK:10] [CK_INV:0]
  • D=[D:10] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:10]
  • FFX_SR_ATTR=[SRLOW:10]
  • LATCH_OR_FF=[FF:10]
  • SYNC_ATTR=[ASYNC:10]
 SLICEM_FFY
  • CE=[CE:8] [CE_INV:0]
  • CK=[CK:16] [CK_INV:0]
  • D=[D:16] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:16]
  • FFY_SR_ATTR=[SRLOW:16]
  • LATCH_OR_FF=[FF:16]
  • SYNC_ATTR=[ASYNC:16]
 SLICEM_G
  • DI=[DI:34] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:8]
  • LUT_OR_MEM=[RAM:34]
 SLICEM_WSGEN
  • CK=[CK:34] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:26]
  • WE=[WE_INV:10] [WE:24]
  • WE0=[WE0:26] [WE0_INV:0]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
 BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
 BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
 IBUF
  • I=3
  • ICLK1=8
  • IQ1=8
  • PAD=11
 IBUF_IFD_DELAY
  • IN=8
  • OUT=8
 IBUF_IFF1
  • CK=8
  • D=8
  • Q=8
 IBUF_INBUF
  • IN=11
  • OUT=11
 IBUF_PAD
  • PAD=11
 IOB
  • I=4
  • O1=19
  • PAD=19
  • T1=4
 IOB_INBUF
  • IN=4
  • OUT=4
 IOB_OUTBUF
  • IN=19
  • OUT=19
  • TRI=4
 IOB_PAD
  • PAD=19
 RAMB16
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • CLKA=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • DOPA1=1
  • ENA=1
  • SSRA=1
  • WEA=1
 RAMB16_RAMB16
  • ADDRA=1
  • DIA=1
  • DOA=1
 RAMB16_RAMB16A
  • ADDRA=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • CLKA=1
  • DIA=1
  • DOA=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • DOPA1=1
  • ENA=1
  • SSRA=1
  • WEA=1
 SLICEL
  • BX=27
  • BY=8
  • CE=8
  • CIN=55
  • CLK=64
  • COUT=56
  • F1=138
  • F2=117
  • F3=93
  • F4=58
  • G1=134
  • G2=113
  • G3=91
  • G4=44
  • SR=30
  • X=59
  • XB=3
  • XQ=51
  • Y=55
  • YQ=52
 SLICEL_C1VDD
  • 1=9
 SLICEL_C2VDD
  • 1=15
 SLICEL_CYMUXF
  • 0=66
  • 1=66
  • OUT=66
  • S0=66
 SLICEL_CYMUXG
  • 0=56
  • 1=56
  • OUT=56
  • S0=56
 SLICEL_F
  • A1=136
  • A2=117
  • A3=93
  • A4=58
  • D=139
 SLICEL_F5MUX
  • F=10
  • G=10
  • OUT=10
  • S0=10
 SLICEL_FAND
  • 0=1
  • 1=1
  • O=1
 SLICEL_FFX
  • CE=5
  • CK=51
  • D=51
  • Q=51
  • SR=24
 SLICEL_FFY
  • CE=8
  • CK=52
  • D=52
  • Q=52
  • SR=21
 SLICEL_G
  • A1=133
  • A2=113
  • A3=91
  • A4=44
  • D=136
 SLICEL_GAND
  • 0=1
  • 1=1
  • O=1
 SLICEL_GNDF
  • 0=48
 SLICEL_GNDG
  • 0=33
 SLICEL_XORF
  • 0=33
  • 1=33
  • O=33
 SLICEL_XORG
  • 0=36
  • 1=36
  • O=36
 SLICEM
  • ALTDIG=8
  • BX=26
  • BY=34
  • BYINVOUT=8
  • BYOUT=8
  • CE=8
  • CLK=34
  • DIG=8
  • F1=34
  • F2=34
  • F3=34
  • F4=34
  • F5=16
  • FXINA=8
  • FXINB=8
  • G1=34
  • G2=34
  • G3=34
  • G4=34
  • SLICEWE1=16
  • SR=34
  • X=8
  • XQ=10
  • Y=8
  • YQ=16
 SLICEM_BYINVOUTUSED
  • 0=8
  • OUT=8
 SLICEM_BYOUTUSED
  • 0=8
  • OUT=8
 SLICEM_DIGUSED
  • 0=8
  • OUT=8
 SLICEM_F
  • A1=34
  • A2=34
  • A3=34
  • A4=34
  • D=34
  • DI=34
  • WF1=34
  • WF2=34
  • WF3=34
  • WF4=34
  • WS=34
 SLICEM_F5MUX
  • F=26
  • G=26
  • OUT=26
  • S0=26
 SLICEM_F6MUX
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
 SLICEM_FFX
  • CK=10
  • D=10
  • Q=10
 SLICEM_FFY
  • CE=8
  • CK=16
  • D=16
  • Q=16
 SLICEM_G
  • A1=34
  • A2=34
  • A3=34
  • A4=34
  • D=34
  • DI=34
  • WG1=34
  • WG2=34
  • WG3=34
  • WG4=34
  • WS=34
 SLICEM_WSGEN
  • CK=34
  • WE=34
  • WE0=26
  • WE1=16
  • WSF=34
  • WSG=34
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 216 178 0 0 0 0 0
bitgen 214 213 0 0 0 0 0
map 289 284 0 0 0 0 0
netgen 14 14 0 0 0 0 0
ngc2edif 84 84 0 0 0 0 0
ngdbuild 330 330 0 0 0 0 0
par 285 266 19 0 0 0 0
trce 268 268 0 0 0 0 0
xpwr 2 2 0 0 0 0 0
xst 737 737 0 0 0 0 0
 
Help Statistics
Search words with results
sra ( 1 )
Help files
/doc/usenglish/isehelp/ite_c_overview.htm ( 2 ) /doc/usenglish/isehelp/ite_r_vhdl_reserved_words.htm ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Board=Spartan-3E Starter Board
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_ProjectDescription=HDL RS-232 Transmitter-Receiver
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/tx_test
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2014-11-28T19:55:11
PROP_intWbtProjectID=2944C65F69701706D045F2C5AFDB20AF PROP_intWbtProjectIteration=37
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_selectedSimRootSourceNode_behav=work.tx_test PROP_xilxBitgStart_IntDone=true
PROP_AutoTop=false PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s500e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=fg320 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VHDL=12
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=74 NGDBUILD_NUM_FDE=11 NGDBUILD_NUM_FDR=30
NGDBUILD_NUM_FDRE=8 NGDBUILD_NUM_FDRSE=10 NGDBUILD_NUM_FDS=2 NGDBUILD_NUM_FDSE=1
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=10 NGDBUILD_NUM_INV=13 NGDBUILD_NUM_IOBUF=4
NGDBUILD_NUM_LD=8 NGDBUILD_NUM_LUT1=36 NGDBUILD_NUM_LUT2=43 NGDBUILD_NUM_LUT2_L=1
NGDBUILD_NUM_LUT3=82 NGDBUILD_NUM_LUT3_D=1 NGDBUILD_NUM_LUT4=108 NGDBUILD_NUM_MULT_AND=2
NGDBUILD_NUM_MUXCY=123 NGDBUILD_NUM_MUXF5=10 NGDBUILD_NUM_OBUF=15 NGDBUILD_NUM_RAM16X1D=8
NGDBUILD_NUM_RAM32X1S=10 NGDBUILD_NUM_RAM64X1S=8 NGDBUILD_NUM_RAMB16_S18=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=69
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=74 NGDBUILD_NUM_FDE=11 NGDBUILD_NUM_FDR=30
NGDBUILD_NUM_FDRE=8 NGDBUILD_NUM_FDRSE=10 NGDBUILD_NUM_FDS=2 NGDBUILD_NUM_FDSE=1
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=14 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=13
NGDBUILD_NUM_LD=8 NGDBUILD_NUM_LUT1=36 NGDBUILD_NUM_LUT2=43 NGDBUILD_NUM_LUT2_L=1
NGDBUILD_NUM_LUT3=82 NGDBUILD_NUM_LUT3_D=1 NGDBUILD_NUM_LUT4=108 NGDBUILD_NUM_MULT_AND=2
NGDBUILD_NUM_MUXCY=123 NGDBUILD_NUM_MUXF5=10 NGDBUILD_NUM_OBUF=15 NGDBUILD_NUM_OBUFT=4
NGDBUILD_NUM_RAM32X1S=10 NGDBUILD_NUM_RAM64X1S=8 NGDBUILD_NUM_RAMB16_S18=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=69
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s500e-4-fg320 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=ieee
Fuse Resource Usage=468 ms, 29908 KB