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-- Company: 
-- Engineer:
--
-- Create Date:   13:22:14 11/29/2014
-- Design Name:   
-- Module Name:   /home/p3t3r/classes/ece446/final_project/RS-232/tx_test.vhd
-- Project Name:  RS-232
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: tx
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tx_test IS
END tx_test;
 
ARCHITECTURE behavior OF tx_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT tx
    PORT(
         clk : IN  std_logic;
         ready : IN  std_logic;
         data : IN  std_logic_vector(7 downto 0);
         tx_line : OUT  std_logic;
         done : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal ready : std_logic := '0';
   signal data : std_logic_vector(7 downto 0) := (others => '0');

 	--Outputs
   signal tx_line : std_logic;
   signal done : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: tx PORT MAP (
          clk => clk,
          ready => ready,
          data => data,
          tx_line => tx_line,
          done => done
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      data <= "01011010";
      wait for clk_period;
      ready <= '1';

      wait for clk_period*3;

      ready <= '0';
      -- insert stimulus here 

      wait;
   end process;

END;