library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity tx is
    Port ( clk : in  STD_LOGIC;
	   ready: in STD_LOGIC;
           data : in  STD_LOGIC_VECTOR (7 downto 0);
	   tx_line : out STD_LOGIC;
           done : out  STD_LOGIC);
end tx;

architecture Behavioral of tx is
type state is (idle, start_bit, bit_0, bit_1, bit_2, bit_3, bit_4, bit_5, bit_6, bit_7, stop_bit);
signal f : state;
signal p : state := idle;

begin
process (clk)
begin
	-- FSM based implementation switches at the clocks
	if rising_edge(clk) then
		p <= f;
	end if;
end process;

process (p,ready, data)
begin
	case p is 
		when idle =>
			--The ready line unlocks the FSM
			--from it's idle state. It exists 
			--to allow the input lines to settle
			tx_line <= '1';
			done <= '1';
			if ready = '1' then
				f <= start_bit;
			else
				f <= idle;
			end if;
		when start_bit =>
			done <= '0';
			tx_line <= '0';
			f <= bit_0;
		when bit_0 =>
			done <= '0';
			tx_line <= data(7);
			f <= bit_1;
		when bit_1 =>
			done <= '0';
			tx_line <= data(6);
			f <= bit_2;
		when bit_2 =>
			tx_line <= data(5);
			f <= bit_3;
			done <= '0';
		when bit_3 =>
			tx_line <= data(4);
			f <= bit_4;
			done <= '0';
		when bit_4 =>
			tx_line <= data(3);
			f <= bit_5;
			done <= '0';
		when bit_5 =>
			tx_line <= data(2);
			f <= bit_6;
			done <= '0';
		when bit_6 =>
			tx_line <= data(1);
			f <= bit_7;
			done <= '0';
		when bit_7 =>
			tx_line <= data(0);
			f <= stop_bit;
			done <= '0';
		when stop_bit =>
			tx_line <= '1';
			f <= idle;
			done <= '0';
		when others =>
		   tx_line <= '1';
			done <= '1';
			f <= idle;
	end case;
end process;

end Behavioral;