rx_tx Project Status (12/02/2014 - 20:34:05) | |||
Project File: | RS-232.xise | Parser Errors: | No Errors |
Module Name: | rx_tx | Implementation State: | Programming File Generated |
Target Device: | xc3s500e-4fg320 |
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No Errors |
Product Version: | ISE 14.6 |
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193 Warnings (0 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 129 | 9,312 | 1% | ||
Number of 4 input LUTs | 306 | 9,312 | 3% | ||
Number of occupied Slices | 186 | 4,656 | 3% | ||
Number of Slices containing only related logic | 186 | 186 | 100% | ||
Number of Slices containing unrelated logic | 0 | 186 | 0% | ||
Total Number of 4 input LUTs | 343 | 9,312 | 3% | ||
Number used as logic | 238 | ||||
Number used as a route-thru | 37 | ||||
Number used for Dual Port RAMs | 16 | ||||
Number used for 32x1 RAMs | 52 | ||||
Number of bonded IOBs | 30 | 232 | 12% | ||
IOB Latches | 8 | ||||
Number of RAMB16s | 1 | 20 | 5% | ||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 3.48 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Tue Dec 2 20:33:21 2014 | 0 | 191 Warnings (0 new) | 11 Infos (0 new) | |
Translation Report | Current | Tue Dec 2 20:33:27 2014 | 0 | 1 Warning (0 new) | 1 Info (0 new) | |
Map Report | Current | Tue Dec 2 20:33:33 2014 | 0 | 0 | 3 Infos (0 new) | |
Place and Route Report | Current | Tue Dec 2 20:33:46 2014 | 0 | 1 Warning (0 new) | 0 | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Tue Dec 2 20:33:50 2014 | 0 | 0 | 5 Infos (0 new) | |
Bitgen Report | Current | Tue Dec 2 20:33:56 2014 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Tue Dec 2 20:25:11 2014 | |
WebTalk Report | Current | Tue Dec 2 20:33:57 2014 | |
WebTalk Log File | Current | Tue Dec 2 20:34:04 2014 |