Release 14.6 Map P.68d (nt64) Xilinx Mapping Report File for Design 'rx_tx' Design Information ------------------ Command Line : map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o rx_tx_map.ncd rx_tx.ngd rx_tx.pcf Target Device : xc3s500e Target Package : fg320 Target Speed : -4 Mapper Version : spartan3e -- $Revision: 1.55 $ Mapped Date : Tue Dec 02 20:33:30 2014 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 129 out of 9,312 1% Number of 4 input LUTs: 306 out of 9,312 3% Logic Distribution: Number of occupied Slices: 186 out of 4,656 3% Number of Slices containing only related logic: 186 out of 186 100% Number of Slices containing unrelated logic: 0 out of 186 0% *See NOTES below for an explanation of the effects of unrelated logic. Total Number of 4 input LUTs: 343 out of 9,312 3% Number used as logic: 238 Number used as a route-thru: 37 Number used for Dual Port RAMs: 16 (Two LUTs used per Dual Port RAM) Number used for 32x1 RAMs: 52 (Two LUTs used per 32x1 RAM) The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. Number of bonded IOBs: 30 out of 232 12% IOB Latches: 8 Number of RAMB16s: 1 out of 20 5% Number of BUFGMUXs: 1 out of 24 4% Average Fanout of Non-Clock Nets: 3.48 Peak Memory Usage: 280 MB Total REAL time to MAP completion: 2 secs Total CPU time to MAP completion: 1 secs NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group and Partition Summary Section 10 - Timing Report Section 11 - Configuration String Information Section 12 - Control Set Information Section 13 - Utilization by Hierarchy Section 1 - Errors ------------------ Section 2 - Warnings -------------------- Section 3 - Informational ------------------------- INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:159 - Net Timing constraints on signal clk are pushed forward through input buffer. INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. Section 4 - Removed Logic Summary --------------------------------- 7 block(s) removed 9 block(s) optimized away 8 signal(s) removed Section 5 - Removed Logic ------------------------- The trimmed logic report below shows the logic removed from your design due to sourceless or loadless signals, and VCC or ground connections. If the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the message explaining that second removal will be indented. This indentation will be repeated as a chain of related logic is removed. To quickly locate the original cause for the removal of a chain of logic, look above the place where that logic is listed in the trimming report, then locate the lines that are least indented (begin at the leftmost edge). Loadless block "lcd_0/processor/read_strobe_flop" (SFF) removed. The signal "lcd_0/processor/read_active" is loadless and has been removed. Loadless block "lcd_0/processor/read_active_lut" (ROM) removed. The trimmed logic reported below is either: 1. part of a cycle 2. part of disabled logic 3. a side-effect of other trimmed logic The signal "lcd_0/processor/int_enable" is unused and has been removed. Unused block "lcd_0/processor/int_enable_flop" (SFF) removed. The signal "lcd_0/processor/int_update_enable" is unused and has been removed. Unused block "lcd_0/processor/int_update_lut" (ROM) removed. The signal "lcd_0/processor/int_enable_value" is unused and has been removed. Unused block "lcd_0/processor/int_value_lut" (ROM) removed. The signal "lcd_0/processor/interrupt_ack_internal" is unused and has been removed. Unused block "lcd_0/processor/ack_flop" (FF) removed. The signal "lcd_0/processor/int_pulse" is unused and has been removed. The signal "lcd_0/processor/not_active_interrupt" is unused and has been removed. The signal "lcd_0/processor/sel_shadow_carry" is unused and has been removed. Unused block "lcd_0/processor/sel_shadow_carry_lut" (ROM) removed. Optimized Block(s): TYPE BLOCK GND XST_GND VCC XST_VCC FDR lcd_0/processor/int_capture_flop optimized to 0 FDR lcd_0/processor/int_flop optimized to 0 LUT4 lcd_0/processor/int_pulse_lut optimized to 0 FDE lcd_0/processor/shadow_carry_flop optimized to 0 FDE lcd_0/processor/shadow_zero_flop optimized to 0 INV lcd_0/processor/stack_count_inv MUXCY lcd_0/processor/sel_shadow_muxcy To enable printing of redundant blocks removed and signals merged, set the detailed map report option and rerun map. Section 6 - IOB Properties -------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Term | Strength | Rate | | | Delay | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | clk | IBUF | INPUT | LVTTL | | | | | | 0 / 0 | | comms_watch | IOB | OUTPUT | LVTTL | | 12 | SLOW | | | 0 / 0 | | din<0> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | | din<1> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | | din<2> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | | din<3> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | | din<4> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | | din<5> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | | din<6> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | | din<7> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 | | dout<0> | IOB | OUTPUT | LVTTL | | 12 | SLOW | | | 0 / 0 | | dout<1> | IOB | OUTPUT | LVTTL | | 12 | SLOW | | | 0 / 0 | | dout<2> | IOB | OUTPUT | LVTTL | | 12 | SLOW | | | 0 / 0 | | dout<3> | IOB | OUTPUT | LVTTL | | 12 | SLOW | | | 0 / 0 | | dout<4> | IOB | OUTPUT | LVTTL | | 12 | SLOW | | | 0 / 0 | | dout<5> | IOB | OUTPUT | LVTTL | | 12 | SLOW | | | 0 / 0 | | dout<6> | IOB | OUTPUT | LVTTL | | 12 | SLOW | | | 0 / 0 | | dout<7> | IOB | OUTPUT | LVTTL | | 12 | SLOW | | | 0 / 0 | | lcd_d<4> | IOB | BIDIR | LVTTL | | 2 | SLOW | | | 0 / 0 | | lcd_d<5> | IOB | BIDIR | LVTTL | | 2 | SLOW | | | 0 / 0 | | lcd_d<6> | IOB | BIDIR | LVTTL | | 2 | SLOW | | | 0 / 0 | | lcd_d<7> | IOB | BIDIR | LVTTL | | 2 | SLOW | | | 0 / 0 | | lcd_e | IOB | OUTPUT | LVTTL | | 2 | SLOW | | | 0 / 0 | | lcd_rs | IOB | OUTPUT | LVTTL | | 2 | SLOW | | | 0 / 0 | | lcd_rw | IOB | OUTPUT | LVTTL | | 2 | SLOW | | | 0 / 0 | | ready_to_transmit | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | speed | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | | strataflash_ce | IOB | OUTPUT | LVTTL | | 2 | SLOW | | | 0 / 0 | | strataflash_oe | IOB | OUTPUT | LVTTL | | 2 | SLOW | | | 0 / 0 | | strataflash_we | IOB | OUTPUT | LVTTL | | 2 | SLOW | | | 0 / 0 | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group and Partition Summary -------------------------------------------- Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Area Group Information ---------------------- No area groups were found in this design. ---------------------- Section 10 - Timing Report -------------------------- This design was not run using timing mode. Section 11 - Configuration String Details ----------------------------------------- Use the "-detail" map option to print out Configuration Strings Section 12 - Control Set Information ------------------------------------ No control set information for this architecture. Section 13 - Utilization by Hierarchy ------------------------------------- Use the "-detail" map option to print out the Utilization by Hierarchy section.