-------------------------------------------------------------------------------- Release 14.6 Trace (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml rx_tx.twx rx_tx.ncd -o rx_tx.twr rx_tx.pcf -ucf LCD_IF.ucf Design file: rx_tx.ncd Physical constraint file: rx_tx.pcf Device,package,speed: xc3s500e,fg320,-4 (PRODUCTION 1.27 2013-06-08) Report level: verbose report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation. INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error. ================================================================================ Timing constraint: NET "clk_BUFGP/IBUFG" PERIOD = 20 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 376597 paths analyzed, 968 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 16.110ns. -------------------------------------------------------------------------------- Paths for end point tx_clk_sel/out_clk (SLICE_X22Y20.F2), 113330 paths -------------------------------------------------------------------------------- Slack (setup path): 3.890ns (requirement - (data path - clock path skew + uncertainty)) Source: tx_clk_sel/count_0 (FF) Destination: tx_clk_sel/out_clk (FF) Requirement: 20.000ns Data Path Delay: 16.110ns (Levels of Logic = 26) Clock Path Skew: 0.000ns Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: tx_clk_sel/count_0 to tx_clk_sel/out_clk Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X18Y6.YQ Tcko 0.652 tx_clk_sel/count<1> tx_clk_sel/count_0 SLICE_X19Y7.F1 net (fanout=1) 0.497 tx_clk_sel/count<0> SLICE_X19Y7.COUT Topcyf 1.162 tx_clk_sel/count_add0000<0> tx_clk_sel/Madd_count_add0000_lut<0>_INV_0 tx_clk_sel/Madd_count_add0000_cy<0> tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.COUT Tbyp 0.118 tx_clk_sel/count_add0000<2> tx_clk_sel/Madd_count_add0000_cy<2> tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.COUT Tbyp 0.118 tx_clk_sel/count_add0000<4> tx_clk_sel/Madd_count_add0000_cy<4> tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.COUT Tbyp 0.118 tx_clk_sel/count_add0000<6> tx_clk_sel/Madd_count_add0000_cy<6> tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.COUT Tbyp 0.118 tx_clk_sel/count_add0000<8> tx_clk_sel/Madd_count_add0000_cy<8> tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.COUT Tbyp 0.118 tx_clk_sel/count_add0000<10> tx_clk_sel/Madd_count_add0000_cy<10> tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.COUT Tbyp 0.118 tx_clk_sel/count_add0000<12> tx_clk_sel/Madd_count_add0000_cy<12> tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.COUT Tbyp 0.118 tx_clk_sel/count_add0000<14> tx_clk_sel/Madd_count_add0000_cy<14> tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.COUT Tbyp 0.118 tx_clk_sel/count_add0000<16> tx_clk_sel/Madd_count_add0000_cy<16> tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.COUT Tbyp 0.118 tx_clk_sel/count_add0000<18> tx_clk_sel/Madd_count_add0000_cy<18> tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.COUT Tbyp 0.118 tx_clk_sel/count_add0000<20> tx_clk_sel/Madd_count_add0000_cy<20> tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.COUT Tbyp 0.118 tx_clk_sel/count_add0000<22> tx_clk_sel/Madd_count_add0000_cy<22> tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.COUT Tbyp 0.118 tx_clk_sel/count_add0000<24> tx_clk_sel/Madd_count_add0000_cy<24> tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.Y Tciny 0.869 tx_clk_sel/count_add0000<26> tx_clk_sel/Madd_count_add0000_cy<26> tx_clk_sel/Madd_count_add0000_xor<27> SLICE_X23Y19.F1 net (fanout=5) 1.039 tx_clk_sel/count_add0000<27> SLICE_X23Y19.XB Topxb 1.176 N45 tx_clk_sel/Mcompar_count_cmp_ge0001_lut<10> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.G3 net (fanout=1) 0.414 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.Y Tilo 0.704 tx_clk_sel/count_mux0003<31> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<12>1 SLICE_X25Y25.G3 net (fanout=68) 1.632 tx_clk_sel/count_mux0002<31>_mand SLICE_X25Y25.COUT Topcyg 1.001 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> tx_clk_sel/Mcompar_count_cmp_ge0002_lut<9> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<10> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.XB Tcinxb 0.404 tx_clk_sel/count_cmp_ge0002 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<12> SLICE_X23Y21.G3 net (fanout=47) 1.447 tx_clk_sel/count_cmp_ge0002 SLICE_X23Y21.COUT Topcyg 1.001 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<3> tx_clk_sel/count_mux0004<5>1 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<3> SLICE_X23Y22.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<3> SLICE_X23Y22.COUT Tbyp 0.118 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<5> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<4> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<5> SLICE_X23Y23.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<5> SLICE_X23Y23.COUT Tbyp 0.118 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<7> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<6> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<7> SLICE_X23Y24.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<7> SLICE_X23Y24.COUT Tbyp 0.118 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<9> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<8> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<9> SLICE_X23Y25.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<9> SLICE_X23Y25.COUT Tbyp 0.118 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<11> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<10> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<11> SLICE_X23Y26.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<11> SLICE_X23Y26.COUT Tbyp 0.118 tx_clk_sel/out_clk_cmp_le0001 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<12> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<13> SLICE_X22Y20.F2 net (fanout=1) 1.096 tx_clk_sel/out_clk_cmp_le0001 SLICE_X22Y20.CLK Tfck 0.892 tx_clk_sel/out_clk tx_clk_sel/out_clk_mux0004 tx_clk_sel/out_clk ------------------------------------------------- --------------------------- Total 16.110ns (9.985ns logic, 6.125ns route) (62.0% logic, 38.0% route) -------------------------------------------------------------------------------- Slack (setup path): 3.923ns (requirement - (data path - clock path skew + uncertainty)) Source: tx_clk_sel/count_0 (FF) Destination: tx_clk_sel/out_clk (FF) Requirement: 20.000ns Data Path Delay: 16.077ns (Levels of Logic = 24) Clock Path Skew: 0.000ns Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: tx_clk_sel/count_0 to tx_clk_sel/out_clk Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X18Y6.YQ Tcko 0.652 tx_clk_sel/count<1> tx_clk_sel/count_0 SLICE_X19Y7.F1 net (fanout=1) 0.497 tx_clk_sel/count<0> SLICE_X19Y7.COUT Topcyf 1.162 tx_clk_sel/count_add0000<0> tx_clk_sel/Madd_count_add0000_lut<0>_INV_0 tx_clk_sel/Madd_count_add0000_cy<0> tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.COUT Tbyp 0.118 tx_clk_sel/count_add0000<2> tx_clk_sel/Madd_count_add0000_cy<2> tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.COUT Tbyp 0.118 tx_clk_sel/count_add0000<4> tx_clk_sel/Madd_count_add0000_cy<4> tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.COUT Tbyp 0.118 tx_clk_sel/count_add0000<6> tx_clk_sel/Madd_count_add0000_cy<6> tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.COUT Tbyp 0.118 tx_clk_sel/count_add0000<8> tx_clk_sel/Madd_count_add0000_cy<8> tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.COUT Tbyp 0.118 tx_clk_sel/count_add0000<10> tx_clk_sel/Madd_count_add0000_cy<10> tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.COUT Tbyp 0.118 tx_clk_sel/count_add0000<12> tx_clk_sel/Madd_count_add0000_cy<12> tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.COUT Tbyp 0.118 tx_clk_sel/count_add0000<14> tx_clk_sel/Madd_count_add0000_cy<14> tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.COUT Tbyp 0.118 tx_clk_sel/count_add0000<16> tx_clk_sel/Madd_count_add0000_cy<16> tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.COUT Tbyp 0.118 tx_clk_sel/count_add0000<18> tx_clk_sel/Madd_count_add0000_cy<18> tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.COUT Tbyp 0.118 tx_clk_sel/count_add0000<20> tx_clk_sel/Madd_count_add0000_cy<20> tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.COUT Tbyp 0.118 tx_clk_sel/count_add0000<22> tx_clk_sel/Madd_count_add0000_cy<22> tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.COUT Tbyp 0.118 tx_clk_sel/count_add0000<24> tx_clk_sel/Madd_count_add0000_cy<24> tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.Y Tciny 0.869 tx_clk_sel/count_add0000<26> tx_clk_sel/Madd_count_add0000_cy<26> tx_clk_sel/Madd_count_add0000_xor<27> SLICE_X23Y19.F1 net (fanout=5) 1.039 tx_clk_sel/count_add0000<27> SLICE_X23Y19.XB Topxb 1.176 N45 tx_clk_sel/Mcompar_count_cmp_ge0001_lut<10> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.G3 net (fanout=1) 0.414 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.Y Tilo 0.704 tx_clk_sel/count_mux0003<31> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<12>1 SLICE_X25Y25.G3 net (fanout=68) 1.632 tx_clk_sel/count_mux0002<31>_mand SLICE_X25Y25.COUT Topcyg 1.001 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> tx_clk_sel/Mcompar_count_cmp_ge0002_lut<9> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<10> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.XB Tcinxb 0.404 tx_clk_sel/count_cmp_ge0002 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<12> SLICE_X23Y23.F2 net (fanout=47) 1.489 tx_clk_sel/count_cmp_ge0002 SLICE_X23Y23.COUT Topcyf 1.162 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<7> tx_clk_sel/Mcompar_out_clk_cmp_le0001_lut<6> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<6> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<7> SLICE_X23Y24.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<7> SLICE_X23Y24.COUT Tbyp 0.118 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<9> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<8> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<9> SLICE_X23Y25.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<9> SLICE_X23Y25.COUT Tbyp 0.118 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<11> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<10> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<11> SLICE_X23Y26.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<11> SLICE_X23Y26.COUT Tbyp 0.118 tx_clk_sel/out_clk_cmp_le0001 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<12> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<13> SLICE_X22Y20.F2 net (fanout=1) 1.096 tx_clk_sel/out_clk_cmp_le0001 SLICE_X22Y20.CLK Tfck 0.892 tx_clk_sel/out_clk tx_clk_sel/out_clk_mux0004 tx_clk_sel/out_clk ------------------------------------------------- --------------------------- Total 16.077ns (9.910ns logic, 6.167ns route) (61.6% logic, 38.4% route) -------------------------------------------------------------------------------- Slack (setup path): 3.923ns (requirement - (data path - clock path skew + uncertainty)) Source: tx_clk_sel/count_0 (FF) Destination: tx_clk_sel/out_clk (FF) Requirement: 20.000ns Data Path Delay: 16.077ns (Levels of Logic = 27) Clock Path Skew: 0.000ns Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: tx_clk_sel/count_0 to tx_clk_sel/out_clk Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X18Y6.YQ Tcko 0.652 tx_clk_sel/count<1> tx_clk_sel/count_0 SLICE_X19Y7.F1 net (fanout=1) 0.497 tx_clk_sel/count<0> SLICE_X19Y7.COUT Topcyf 1.162 tx_clk_sel/count_add0000<0> tx_clk_sel/Madd_count_add0000_lut<0>_INV_0 tx_clk_sel/Madd_count_add0000_cy<0> tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.COUT Tbyp 0.118 tx_clk_sel/count_add0000<2> tx_clk_sel/Madd_count_add0000_cy<2> tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.COUT Tbyp 0.118 tx_clk_sel/count_add0000<4> tx_clk_sel/Madd_count_add0000_cy<4> tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.COUT Tbyp 0.118 tx_clk_sel/count_add0000<6> tx_clk_sel/Madd_count_add0000_cy<6> tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.COUT Tbyp 0.118 tx_clk_sel/count_add0000<8> tx_clk_sel/Madd_count_add0000_cy<8> tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.COUT Tbyp 0.118 tx_clk_sel/count_add0000<10> tx_clk_sel/Madd_count_add0000_cy<10> tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.COUT Tbyp 0.118 tx_clk_sel/count_add0000<12> tx_clk_sel/Madd_count_add0000_cy<12> tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.COUT Tbyp 0.118 tx_clk_sel/count_add0000<14> tx_clk_sel/Madd_count_add0000_cy<14> tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.COUT Tbyp 0.118 tx_clk_sel/count_add0000<16> tx_clk_sel/Madd_count_add0000_cy<16> tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.COUT Tbyp 0.118 tx_clk_sel/count_add0000<18> tx_clk_sel/Madd_count_add0000_cy<18> tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.COUT Tbyp 0.118 tx_clk_sel/count_add0000<20> tx_clk_sel/Madd_count_add0000_cy<20> tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.COUT Tbyp 0.118 tx_clk_sel/count_add0000<22> tx_clk_sel/Madd_count_add0000_cy<22> tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.COUT Tbyp 0.118 tx_clk_sel/count_add0000<24> tx_clk_sel/Madd_count_add0000_cy<24> tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.Y Tciny 0.869 tx_clk_sel/count_add0000<26> tx_clk_sel/Madd_count_add0000_cy<26> tx_clk_sel/Madd_count_add0000_xor<27> SLICE_X23Y19.F1 net (fanout=5) 1.039 tx_clk_sel/count_add0000<27> SLICE_X23Y19.XB Topxb 1.176 N45 tx_clk_sel/Mcompar_count_cmp_ge0001_lut<10> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.G3 net (fanout=1) 0.414 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.Y Tilo 0.704 tx_clk_sel/count_mux0003<31> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<12>1 SLICE_X25Y24.F4 net (fanout=68) 1.320 tx_clk_sel/count_mux0002<31>_mand SLICE_X25Y24.COUT Topcyf 1.162 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<7> tx_clk_sel/count_mux0003<12>1 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<6> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<7> SLICE_X25Y25.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<7> SLICE_X25Y25.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<8> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<10> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.XB Tcinxb 0.404 tx_clk_sel/count_cmp_ge0002 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<12> SLICE_X23Y21.G3 net (fanout=47) 1.447 tx_clk_sel/count_cmp_ge0002 SLICE_X23Y21.COUT Topcyg 1.001 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<3> tx_clk_sel/count_mux0004<5>1 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<3> SLICE_X23Y22.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<3> SLICE_X23Y22.COUT Tbyp 0.118 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<5> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<4> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<5> SLICE_X23Y23.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<5> SLICE_X23Y23.COUT Tbyp 0.118 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<7> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<6> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<7> SLICE_X23Y24.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<7> SLICE_X23Y24.COUT Tbyp 0.118 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<9> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<8> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<9> SLICE_X23Y25.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<9> SLICE_X23Y25.COUT Tbyp 0.118 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<11> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<10> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<11> SLICE_X23Y26.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<11> SLICE_X23Y26.COUT Tbyp 0.118 tx_clk_sel/out_clk_cmp_le0001 tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<12> tx_clk_sel/Mcompar_out_clk_cmp_le0001_cy<13> SLICE_X22Y20.F2 net (fanout=1) 1.096 tx_clk_sel/out_clk_cmp_le0001 SLICE_X22Y20.CLK Tfck 0.892 tx_clk_sel/out_clk tx_clk_sel/out_clk_mux0004 tx_clk_sel/out_clk ------------------------------------------------- --------------------------- Total 16.077ns (10.264ns logic, 5.813ns route) (63.8% logic, 36.2% route) -------------------------------------------------------------------------------- Paths for end point tx_clk_sel/count_4 (SLICE_X18Y9.G2), 7018 paths -------------------------------------------------------------------------------- Slack (setup path): 5.292ns (requirement - (data path - clock path skew + uncertainty)) Source: tx_clk_sel/count_0 (FF) Destination: tx_clk_sel/count_4 (FF) Requirement: 20.000ns Data Path Delay: 14.705ns (Levels of Logic = 20) Clock Path Skew: -0.003ns (0.008 - 0.011) Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: tx_clk_sel/count_0 to tx_clk_sel/count_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X18Y6.YQ Tcko 0.652 tx_clk_sel/count<1> tx_clk_sel/count_0 SLICE_X19Y7.F1 net (fanout=1) 0.497 tx_clk_sel/count<0> SLICE_X19Y7.COUT Topcyf 1.162 tx_clk_sel/count_add0000<0> tx_clk_sel/Madd_count_add0000_lut<0>_INV_0 tx_clk_sel/Madd_count_add0000_cy<0> tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.COUT Tbyp 0.118 tx_clk_sel/count_add0000<2> tx_clk_sel/Madd_count_add0000_cy<2> tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.COUT Tbyp 0.118 tx_clk_sel/count_add0000<4> tx_clk_sel/Madd_count_add0000_cy<4> tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.COUT Tbyp 0.118 tx_clk_sel/count_add0000<6> tx_clk_sel/Madd_count_add0000_cy<6> tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.COUT Tbyp 0.118 tx_clk_sel/count_add0000<8> tx_clk_sel/Madd_count_add0000_cy<8> tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.COUT Tbyp 0.118 tx_clk_sel/count_add0000<10> tx_clk_sel/Madd_count_add0000_cy<10> tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.COUT Tbyp 0.118 tx_clk_sel/count_add0000<12> tx_clk_sel/Madd_count_add0000_cy<12> tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.COUT Tbyp 0.118 tx_clk_sel/count_add0000<14> tx_clk_sel/Madd_count_add0000_cy<14> tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.COUT Tbyp 0.118 tx_clk_sel/count_add0000<16> tx_clk_sel/Madd_count_add0000_cy<16> tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.COUT Tbyp 0.118 tx_clk_sel/count_add0000<18> tx_clk_sel/Madd_count_add0000_cy<18> tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.COUT Tbyp 0.118 tx_clk_sel/count_add0000<20> tx_clk_sel/Madd_count_add0000_cy<20> tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.COUT Tbyp 0.118 tx_clk_sel/count_add0000<22> tx_clk_sel/Madd_count_add0000_cy<22> tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.COUT Tbyp 0.118 tx_clk_sel/count_add0000<24> tx_clk_sel/Madd_count_add0000_cy<24> tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.Y Tciny 0.869 tx_clk_sel/count_add0000<26> tx_clk_sel/Madd_count_add0000_cy<26> tx_clk_sel/Madd_count_add0000_xor<27> SLICE_X23Y19.F1 net (fanout=5) 1.039 tx_clk_sel/count_add0000<27> SLICE_X23Y19.XB Topxb 1.176 N45 tx_clk_sel/Mcompar_count_cmp_ge0001_lut<10> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.G3 net (fanout=1) 0.414 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.Y Tilo 0.704 tx_clk_sel/count_mux0003<31> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<12>1 SLICE_X25Y25.G3 net (fanout=68) 1.632 tx_clk_sel/count_mux0002<31>_mand SLICE_X25Y25.COUT Topcyg 1.001 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> tx_clk_sel/Mcompar_count_cmp_ge0002_lut<9> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<10> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.XB Tcinxb 0.404 tx_clk_sel/count_cmp_ge0002 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<12> SLICE_X18Y9.G2 net (fanout=47) 2.729 tx_clk_sel/count_cmp_ge0002 SLICE_X18Y9.CLK Tgck 0.892 tx_clk_sel/count<5> tx_clk_sel/count_mux0008<4>1 tx_clk_sel/count_4 ------------------------------------------------- --------------------------- Total 14.705ns (8.394ns logic, 6.311ns route) (57.1% logic, 42.9% route) -------------------------------------------------------------------------------- Slack (setup path): 5.325ns (requirement - (data path - clock path skew + uncertainty)) Source: tx_clk_sel/count_0 (FF) Destination: tx_clk_sel/count_4 (FF) Requirement: 20.000ns Data Path Delay: 14.672ns (Levels of Logic = 21) Clock Path Skew: -0.003ns (0.008 - 0.011) Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: tx_clk_sel/count_0 to tx_clk_sel/count_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X18Y6.YQ Tcko 0.652 tx_clk_sel/count<1> tx_clk_sel/count_0 SLICE_X19Y7.F1 net (fanout=1) 0.497 tx_clk_sel/count<0> SLICE_X19Y7.COUT Topcyf 1.162 tx_clk_sel/count_add0000<0> tx_clk_sel/Madd_count_add0000_lut<0>_INV_0 tx_clk_sel/Madd_count_add0000_cy<0> tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.COUT Tbyp 0.118 tx_clk_sel/count_add0000<2> tx_clk_sel/Madd_count_add0000_cy<2> tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.COUT Tbyp 0.118 tx_clk_sel/count_add0000<4> tx_clk_sel/Madd_count_add0000_cy<4> tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.COUT Tbyp 0.118 tx_clk_sel/count_add0000<6> tx_clk_sel/Madd_count_add0000_cy<6> tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.COUT Tbyp 0.118 tx_clk_sel/count_add0000<8> tx_clk_sel/Madd_count_add0000_cy<8> tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.COUT Tbyp 0.118 tx_clk_sel/count_add0000<10> tx_clk_sel/Madd_count_add0000_cy<10> tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.COUT Tbyp 0.118 tx_clk_sel/count_add0000<12> tx_clk_sel/Madd_count_add0000_cy<12> tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.COUT Tbyp 0.118 tx_clk_sel/count_add0000<14> tx_clk_sel/Madd_count_add0000_cy<14> tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.COUT Tbyp 0.118 tx_clk_sel/count_add0000<16> tx_clk_sel/Madd_count_add0000_cy<16> tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.COUT Tbyp 0.118 tx_clk_sel/count_add0000<18> tx_clk_sel/Madd_count_add0000_cy<18> tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.COUT Tbyp 0.118 tx_clk_sel/count_add0000<20> tx_clk_sel/Madd_count_add0000_cy<20> tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.COUT Tbyp 0.118 tx_clk_sel/count_add0000<22> tx_clk_sel/Madd_count_add0000_cy<22> tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.COUT Tbyp 0.118 tx_clk_sel/count_add0000<24> tx_clk_sel/Madd_count_add0000_cy<24> tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.Y Tciny 0.869 tx_clk_sel/count_add0000<26> tx_clk_sel/Madd_count_add0000_cy<26> tx_clk_sel/Madd_count_add0000_xor<27> SLICE_X23Y19.F1 net (fanout=5) 1.039 tx_clk_sel/count_add0000<27> SLICE_X23Y19.XB Topxb 1.176 N45 tx_clk_sel/Mcompar_count_cmp_ge0001_lut<10> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.G3 net (fanout=1) 0.414 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.Y Tilo 0.704 tx_clk_sel/count_mux0003<31> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<12>1 SLICE_X25Y24.F4 net (fanout=68) 1.320 tx_clk_sel/count_mux0002<31>_mand SLICE_X25Y24.COUT Topcyf 1.162 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<7> tx_clk_sel/count_mux0003<12>1 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<6> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<7> SLICE_X25Y25.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<7> SLICE_X25Y25.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<8> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<10> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.XB Tcinxb 0.404 tx_clk_sel/count_cmp_ge0002 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<12> SLICE_X18Y9.G2 net (fanout=47) 2.729 tx_clk_sel/count_cmp_ge0002 SLICE_X18Y9.CLK Tgck 0.892 tx_clk_sel/count<5> tx_clk_sel/count_mux0008<4>1 tx_clk_sel/count_4 ------------------------------------------------- --------------------------- Total 14.672ns (8.673ns logic, 5.999ns route) (59.1% logic, 40.9% route) -------------------------------------------------------------------------------- Slack (setup path): 5.382ns (requirement - (data path - clock path skew + uncertainty)) Source: tx_clk_sel/count_0 (FF) Destination: tx_clk_sel/count_4 (FF) Requirement: 20.000ns Data Path Delay: 14.615ns (Levels of Logic = 19) Clock Path Skew: -0.003ns (0.008 - 0.011) Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: tx_clk_sel/count_0 to tx_clk_sel/count_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X18Y6.YQ Tcko 0.652 tx_clk_sel/count<1> tx_clk_sel/count_0 SLICE_X19Y7.F1 net (fanout=1) 0.497 tx_clk_sel/count<0> SLICE_X19Y7.COUT Topcyf 1.162 tx_clk_sel/count_add0000<0> tx_clk_sel/Madd_count_add0000_lut<0>_INV_0 tx_clk_sel/Madd_count_add0000_cy<0> tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.COUT Tbyp 0.118 tx_clk_sel/count_add0000<2> tx_clk_sel/Madd_count_add0000_cy<2> tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.COUT Tbyp 0.118 tx_clk_sel/count_add0000<4> tx_clk_sel/Madd_count_add0000_cy<4> tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.COUT Tbyp 0.118 tx_clk_sel/count_add0000<6> tx_clk_sel/Madd_count_add0000_cy<6> tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.COUT Tbyp 0.118 tx_clk_sel/count_add0000<8> tx_clk_sel/Madd_count_add0000_cy<8> tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.COUT Tbyp 0.118 tx_clk_sel/count_add0000<10> tx_clk_sel/Madd_count_add0000_cy<10> tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.COUT Tbyp 0.118 tx_clk_sel/count_add0000<12> tx_clk_sel/Madd_count_add0000_cy<12> tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.COUT Tbyp 0.118 tx_clk_sel/count_add0000<14> tx_clk_sel/Madd_count_add0000_cy<14> tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.COUT Tbyp 0.118 tx_clk_sel/count_add0000<16> tx_clk_sel/Madd_count_add0000_cy<16> tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.COUT Tbyp 0.118 tx_clk_sel/count_add0000<18> tx_clk_sel/Madd_count_add0000_cy<18> tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.Y Tciny 0.869 tx_clk_sel/count_add0000<20> tx_clk_sel/Madd_count_add0000_cy<20> tx_clk_sel/Madd_count_add0000_xor<21> SLICE_X23Y17.F1 net (fanout=5) 0.795 tx_clk_sel/count_add0000<21> SLICE_X23Y17.COUT Topcyf 1.162 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<7> tx_clk_sel/Mcompar_count_cmp_ge0001_lut<6> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<6> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<7> SLICE_X23Y18.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<7> SLICE_X23Y18.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<9> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<8> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<9> SLICE_X23Y19.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<9> SLICE_X23Y19.XB Tcinxb 0.404 N45 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.G3 net (fanout=1) 0.414 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.Y Tilo 0.704 tx_clk_sel/count_mux0003<31> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<12>1 SLICE_X25Y25.G3 net (fanout=68) 1.632 tx_clk_sel/count_mux0002<31>_mand SLICE_X25Y25.COUT Topcyg 1.001 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> tx_clk_sel/Mcompar_count_cmp_ge0002_lut<9> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<10> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.XB Tcinxb 0.404 tx_clk_sel/count_cmp_ge0002 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<12> SLICE_X18Y9.G2 net (fanout=47) 2.729 tx_clk_sel/count_cmp_ge0002 SLICE_X18Y9.CLK Tgck 0.892 tx_clk_sel/count<5> tx_clk_sel/count_mux0008<4>1 tx_clk_sel/count_4 ------------------------------------------------- --------------------------- Total 14.615ns (8.548ns logic, 6.067ns route) (58.5% logic, 41.5% route) -------------------------------------------------------------------------------- Paths for end point tx_clk_sel/count_5 (SLICE_X18Y9.F2), 7018 paths -------------------------------------------------------------------------------- Slack (setup path): 5.332ns (requirement - (data path - clock path skew + uncertainty)) Source: tx_clk_sel/count_0 (FF) Destination: tx_clk_sel/count_5 (FF) Requirement: 20.000ns Data Path Delay: 14.665ns (Levels of Logic = 20) Clock Path Skew: -0.003ns (0.008 - 0.011) Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: tx_clk_sel/count_0 to tx_clk_sel/count_5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X18Y6.YQ Tcko 0.652 tx_clk_sel/count<1> tx_clk_sel/count_0 SLICE_X19Y7.F1 net (fanout=1) 0.497 tx_clk_sel/count<0> SLICE_X19Y7.COUT Topcyf 1.162 tx_clk_sel/count_add0000<0> tx_clk_sel/Madd_count_add0000_lut<0>_INV_0 tx_clk_sel/Madd_count_add0000_cy<0> tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.COUT Tbyp 0.118 tx_clk_sel/count_add0000<2> tx_clk_sel/Madd_count_add0000_cy<2> tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.COUT Tbyp 0.118 tx_clk_sel/count_add0000<4> tx_clk_sel/Madd_count_add0000_cy<4> tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.COUT Tbyp 0.118 tx_clk_sel/count_add0000<6> tx_clk_sel/Madd_count_add0000_cy<6> tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.COUT Tbyp 0.118 tx_clk_sel/count_add0000<8> tx_clk_sel/Madd_count_add0000_cy<8> tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.COUT Tbyp 0.118 tx_clk_sel/count_add0000<10> tx_clk_sel/Madd_count_add0000_cy<10> tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.COUT Tbyp 0.118 tx_clk_sel/count_add0000<12> tx_clk_sel/Madd_count_add0000_cy<12> tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.COUT Tbyp 0.118 tx_clk_sel/count_add0000<14> tx_clk_sel/Madd_count_add0000_cy<14> tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.COUT Tbyp 0.118 tx_clk_sel/count_add0000<16> tx_clk_sel/Madd_count_add0000_cy<16> tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.COUT Tbyp 0.118 tx_clk_sel/count_add0000<18> tx_clk_sel/Madd_count_add0000_cy<18> tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.COUT Tbyp 0.118 tx_clk_sel/count_add0000<20> tx_clk_sel/Madd_count_add0000_cy<20> tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.COUT Tbyp 0.118 tx_clk_sel/count_add0000<22> tx_clk_sel/Madd_count_add0000_cy<22> tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.COUT Tbyp 0.118 tx_clk_sel/count_add0000<24> tx_clk_sel/Madd_count_add0000_cy<24> tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.Y Tciny 0.869 tx_clk_sel/count_add0000<26> tx_clk_sel/Madd_count_add0000_cy<26> tx_clk_sel/Madd_count_add0000_xor<27> SLICE_X23Y19.F1 net (fanout=5) 1.039 tx_clk_sel/count_add0000<27> SLICE_X23Y19.XB Topxb 1.176 N45 tx_clk_sel/Mcompar_count_cmp_ge0001_lut<10> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.G3 net (fanout=1) 0.414 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.Y Tilo 0.704 tx_clk_sel/count_mux0003<31> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<12>1 SLICE_X25Y25.G3 net (fanout=68) 1.632 tx_clk_sel/count_mux0002<31>_mand SLICE_X25Y25.COUT Topcyg 1.001 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> tx_clk_sel/Mcompar_count_cmp_ge0002_lut<9> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<10> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.XB Tcinxb 0.404 tx_clk_sel/count_cmp_ge0002 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<12> SLICE_X18Y9.F2 net (fanout=47) 2.689 tx_clk_sel/count_cmp_ge0002 SLICE_X18Y9.CLK Tfck 0.892 tx_clk_sel/count<5> tx_clk_sel/count_mux0008<5>1 tx_clk_sel/count_5 ------------------------------------------------- --------------------------- Total 14.665ns (8.394ns logic, 6.271ns route) (57.2% logic, 42.8% route) -------------------------------------------------------------------------------- Slack (setup path): 5.365ns (requirement - (data path - clock path skew + uncertainty)) Source: tx_clk_sel/count_0 (FF) Destination: tx_clk_sel/count_5 (FF) Requirement: 20.000ns Data Path Delay: 14.632ns (Levels of Logic = 21) Clock Path Skew: -0.003ns (0.008 - 0.011) Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: tx_clk_sel/count_0 to tx_clk_sel/count_5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X18Y6.YQ Tcko 0.652 tx_clk_sel/count<1> tx_clk_sel/count_0 SLICE_X19Y7.F1 net (fanout=1) 0.497 tx_clk_sel/count<0> SLICE_X19Y7.COUT Topcyf 1.162 tx_clk_sel/count_add0000<0> tx_clk_sel/Madd_count_add0000_lut<0>_INV_0 tx_clk_sel/Madd_count_add0000_cy<0> tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.COUT Tbyp 0.118 tx_clk_sel/count_add0000<2> tx_clk_sel/Madd_count_add0000_cy<2> tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.COUT Tbyp 0.118 tx_clk_sel/count_add0000<4> tx_clk_sel/Madd_count_add0000_cy<4> tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.COUT Tbyp 0.118 tx_clk_sel/count_add0000<6> tx_clk_sel/Madd_count_add0000_cy<6> tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.COUT Tbyp 0.118 tx_clk_sel/count_add0000<8> tx_clk_sel/Madd_count_add0000_cy<8> tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.COUT Tbyp 0.118 tx_clk_sel/count_add0000<10> tx_clk_sel/Madd_count_add0000_cy<10> tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.COUT Tbyp 0.118 tx_clk_sel/count_add0000<12> tx_clk_sel/Madd_count_add0000_cy<12> tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.COUT Tbyp 0.118 tx_clk_sel/count_add0000<14> tx_clk_sel/Madd_count_add0000_cy<14> tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.COUT Tbyp 0.118 tx_clk_sel/count_add0000<16> tx_clk_sel/Madd_count_add0000_cy<16> tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.COUT Tbyp 0.118 tx_clk_sel/count_add0000<18> tx_clk_sel/Madd_count_add0000_cy<18> tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.COUT Tbyp 0.118 tx_clk_sel/count_add0000<20> tx_clk_sel/Madd_count_add0000_cy<20> tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<21> SLICE_X19Y18.COUT Tbyp 0.118 tx_clk_sel/count_add0000<22> tx_clk_sel/Madd_count_add0000_cy<22> tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<23> SLICE_X19Y19.COUT Tbyp 0.118 tx_clk_sel/count_add0000<24> tx_clk_sel/Madd_count_add0000_cy<24> tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<25> SLICE_X19Y20.Y Tciny 0.869 tx_clk_sel/count_add0000<26> tx_clk_sel/Madd_count_add0000_cy<26> tx_clk_sel/Madd_count_add0000_xor<27> SLICE_X23Y19.F1 net (fanout=5) 1.039 tx_clk_sel/count_add0000<27> SLICE_X23Y19.XB Topxb 1.176 N45 tx_clk_sel/Mcompar_count_cmp_ge0001_lut<10> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.G3 net (fanout=1) 0.414 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.Y Tilo 0.704 tx_clk_sel/count_mux0003<31> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<12>1 SLICE_X25Y24.F4 net (fanout=68) 1.320 tx_clk_sel/count_mux0002<31>_mand SLICE_X25Y24.COUT Topcyf 1.162 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<7> tx_clk_sel/count_mux0003<12>1 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<6> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<7> SLICE_X25Y25.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<7> SLICE_X25Y25.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<8> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<10> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.XB Tcinxb 0.404 tx_clk_sel/count_cmp_ge0002 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<12> SLICE_X18Y9.F2 net (fanout=47) 2.689 tx_clk_sel/count_cmp_ge0002 SLICE_X18Y9.CLK Tfck 0.892 tx_clk_sel/count<5> tx_clk_sel/count_mux0008<5>1 tx_clk_sel/count_5 ------------------------------------------------- --------------------------- Total 14.632ns (8.673ns logic, 5.959ns route) (59.3% logic, 40.7% route) -------------------------------------------------------------------------------- Slack (setup path): 5.422ns (requirement - (data path - clock path skew + uncertainty)) Source: tx_clk_sel/count_0 (FF) Destination: tx_clk_sel/count_5 (FF) Requirement: 20.000ns Data Path Delay: 14.575ns (Levels of Logic = 19) Clock Path Skew: -0.003ns (0.008 - 0.011) Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Maximum Data Path: tx_clk_sel/count_0 to tx_clk_sel/count_5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X18Y6.YQ Tcko 0.652 tx_clk_sel/count<1> tx_clk_sel/count_0 SLICE_X19Y7.F1 net (fanout=1) 0.497 tx_clk_sel/count<0> SLICE_X19Y7.COUT Topcyf 1.162 tx_clk_sel/count_add0000<0> tx_clk_sel/Madd_count_add0000_lut<0>_INV_0 tx_clk_sel/Madd_count_add0000_cy<0> tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<1> SLICE_X19Y8.COUT Tbyp 0.118 tx_clk_sel/count_add0000<2> tx_clk_sel/Madd_count_add0000_cy<2> tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<3> SLICE_X19Y9.COUT Tbyp 0.118 tx_clk_sel/count_add0000<4> tx_clk_sel/Madd_count_add0000_cy<4> tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<5> SLICE_X19Y10.COUT Tbyp 0.118 tx_clk_sel/count_add0000<6> tx_clk_sel/Madd_count_add0000_cy<6> tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<7> SLICE_X19Y11.COUT Tbyp 0.118 tx_clk_sel/count_add0000<8> tx_clk_sel/Madd_count_add0000_cy<8> tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<9> SLICE_X19Y12.COUT Tbyp 0.118 tx_clk_sel/count_add0000<10> tx_clk_sel/Madd_count_add0000_cy<10> tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<11> SLICE_X19Y13.COUT Tbyp 0.118 tx_clk_sel/count_add0000<12> tx_clk_sel/Madd_count_add0000_cy<12> tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<13> SLICE_X19Y14.COUT Tbyp 0.118 tx_clk_sel/count_add0000<14> tx_clk_sel/Madd_count_add0000_cy<14> tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<15> SLICE_X19Y15.COUT Tbyp 0.118 tx_clk_sel/count_add0000<16> tx_clk_sel/Madd_count_add0000_cy<16> tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<17> SLICE_X19Y16.COUT Tbyp 0.118 tx_clk_sel/count_add0000<18> tx_clk_sel/Madd_count_add0000_cy<18> tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.CIN net (fanout=1) 0.000 tx_clk_sel/Madd_count_add0000_cy<19> SLICE_X19Y17.Y Tciny 0.869 tx_clk_sel/count_add0000<20> tx_clk_sel/Madd_count_add0000_cy<20> tx_clk_sel/Madd_count_add0000_xor<21> SLICE_X23Y17.F1 net (fanout=5) 0.795 tx_clk_sel/count_add0000<21> SLICE_X23Y17.COUT Topcyf 1.162 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<7> tx_clk_sel/Mcompar_count_cmp_ge0001_lut<6> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<6> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<7> SLICE_X23Y18.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<7> SLICE_X23Y18.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<9> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<8> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<9> SLICE_X23Y19.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<9> SLICE_X23Y19.XB Tcinxb 0.404 N45 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.G3 net (fanout=1) 0.414 tx_clk_sel/Mcompar_count_cmp_ge0001_cy<10> SLICE_X25Y20.Y Tilo 0.704 tx_clk_sel/count_mux0003<31> tx_clk_sel/Mcompar_count_cmp_ge0001_cy<12>1 SLICE_X25Y25.G3 net (fanout=68) 1.632 tx_clk_sel/count_mux0002<31>_mand SLICE_X25Y25.COUT Topcyg 1.001 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> tx_clk_sel/Mcompar_count_cmp_ge0002_lut<9> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<9> SLICE_X25Y26.COUT Tbyp 0.118 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<10> tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.CIN net (fanout=1) 0.000 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<11> SLICE_X25Y27.XB Tcinxb 0.404 tx_clk_sel/count_cmp_ge0002 tx_clk_sel/Mcompar_count_cmp_ge0002_cy<12> SLICE_X18Y9.F2 net (fanout=47) 2.689 tx_clk_sel/count_cmp_ge0002 SLICE_X18Y9.CLK Tfck 0.892 tx_clk_sel/count<5> tx_clk_sel/count_mux0008<5>1 tx_clk_sel/count_5 ------------------------------------------------- --------------------------- Total 14.575ns (8.548ns logic, 6.027ns route) (58.6% logic, 41.4% route) -------------------------------------------------------------------------------- Hold Paths: NET "clk_BUFGP/IBUFG" PERIOD = 20 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point lcd_0/processor/stack_ram_loop[4].stack_bit/G (SLICE_X46Y37.BY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.746ns (requirement - (clock path skew + uncertainty - data path)) Source: lcd_0/processor/pc_loop[4].register_bit (FF) Destination: lcd_0/processor/stack_ram_loop[4].stack_bit/G (RAM) Requirement: 0.000ns Data Path Delay: 0.754ns (Levels of Logic = 1) Clock Path Skew: 0.008ns (0.023 - 0.015) Source Clock: clk_BUFGP rising at 20.000ns Destination Clock: clk_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Minimum Data Path: lcd_0/processor/pc_loop[4].register_bit to lcd_0/processor/stack_ram_loop[4].stack_bit/G Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X49Y35.XQ Tcko 0.473 lcd_0/address<4> lcd_0/processor/pc_loop[4].register_bit SLICE_X46Y37.BY net (fanout=3) 0.408 lcd_0/address<4> SLICE_X46Y37.CLK Tdh (-Th) 0.127 lcd_0/processor/stack_pop_data<4> lcd_0/processor/stack_ram_loop[4].stack_bit/G ------------------------------------------------- --------------------------- Total 0.754ns (0.346ns logic, 0.408ns route) (45.9% logic, 54.1% route) -------------------------------------------------------------------------------- Paths for end point lcd_0/processor/stack_ram_loop[9].stack_bit/G (SLICE_X50Y36.BY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.750ns (requirement - (clock path skew + uncertainty - data path)) Source: lcd_0/processor/pc_loop[9].register_bit (FF) Destination: lcd_0/processor/stack_ram_loop[9].stack_bit/G (RAM) Requirement: 0.000ns Data Path Delay: 0.751ns (Levels of Logic = 1) Clock Path Skew: 0.001ns (0.063 - 0.062) Source Clock: clk_BUFGP rising at 20.000ns Destination Clock: clk_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Minimum Data Path: lcd_0/processor/pc_loop[9].register_bit to lcd_0/processor/stack_ram_loop[9].stack_bit/G Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X49Y37.YQ Tcko 0.470 lcd_0/address<8> lcd_0/processor/pc_loop[9].register_bit SLICE_X50Y36.BY net (fanout=3) 0.408 lcd_0/address<9> SLICE_X50Y36.CLK Tdh (-Th) 0.127 lcd_0/processor/stack_pop_data<9> lcd_0/processor/stack_ram_loop[9].stack_bit/G ------------------------------------------------- --------------------------- Total 0.751ns (0.343ns logic, 0.408ns route) (45.7% logic, 54.3% route) -------------------------------------------------------------------------------- Paths for end point lcd_0/processor/stack_ram_loop[4].stack_bit/F (SLICE_X46Y37.BY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.761ns (requirement - (clock path skew + uncertainty - data path)) Source: lcd_0/processor/pc_loop[4].register_bit (FF) Destination: lcd_0/processor/stack_ram_loop[4].stack_bit/F (RAM) Requirement: 0.000ns Data Path Delay: 0.769ns (Levels of Logic = 1) Clock Path Skew: 0.008ns (0.023 - 0.015) Source Clock: clk_BUFGP rising at 20.000ns Destination Clock: clk_BUFGP rising at 20.000ns Clock Uncertainty: 0.000ns Minimum Data Path: lcd_0/processor/pc_loop[4].register_bit to lcd_0/processor/stack_ram_loop[4].stack_bit/F Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X49Y35.XQ Tcko 0.473 lcd_0/address<4> lcd_0/processor/pc_loop[4].register_bit SLICE_X46Y37.BY net (fanout=3) 0.408 lcd_0/address<4> SLICE_X46Y37.CLK Tdh (-Th) 0.112 lcd_0/processor/stack_pop_data<4> lcd_0/processor/stack_ram_loop[4].stack_bit/F ------------------------------------------------- --------------------------- Total 0.769ns (0.361ns logic, 0.408ns route) (46.9% logic, 53.1% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: NET "clk_BUFGP/IBUFG" PERIOD = 20 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 16.824ns (period - (min low pulse limit / (low pulse / period))) Period: 20.000ns Low pulse: 10.000ns Low pulse limit: 1.588ns (Tbpwl) Physical resource: lcd_0/program_rom/ram_1024_x_18/CLKA Logical resource: lcd_0/program_rom/ram_1024_x_18.A/CLKA Location pin: RAMB16_X1Y4.CLKA Clock network: clk_BUFGP -------------------------------------------------------------------------------- Slack: 16.824ns (period - (min high pulse limit / (high pulse / period))) Period: 20.000ns High pulse: 10.000ns High pulse limit: 1.588ns (Tbpwh) Physical resource: lcd_0/program_rom/ram_1024_x_18/CLKA Logical resource: lcd_0/program_rom/ram_1024_x_18.A/CLKA Location pin: RAMB16_X1Y4.CLKA Clock network: clk_BUFGP -------------------------------------------------------------------------------- Slack: 16.824ns (period - min period limit) Period: 20.000ns Min period limit: 3.176ns (314.861MHz) (Tbp) Physical resource: lcd_0/program_rom/ram_1024_x_18/CLKA Logical resource: lcd_0/program_rom/ram_1024_x_18.A/CLKA Location pin: RAMB16_X1Y4.CLKA Clock network: clk_BUFGP -------------------------------------------------------------------------------- All constraints were met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Clock to Setup on destination clock clk ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk | 16.110| | | | ---------------+---------+---------+---------+---------+ Timing summary: --------------- Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) Constraints cover 376597 paths, 0 nets, and 1308 connections Design statistics: Minimum period: 16.110ns{1} (Maximum frequency: 62.073MHz) ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. Analysis completed Tue Dec 02 20:33:49 2014 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 174 MB