--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:08:36 11/29/2014
-- Design Name:   
-- Module Name:   /home/p3t3r/classes/ece446/final_project/RS-232/rx_test.vhd
-- Project Name:  RS-232
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: rx
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY rx_test IS
END rx_test;
 
ARCHITECTURE behavior OF rx_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT rx
    PORT(
         rx_line : IN  std_logic;
         clk : IN  std_logic;
         err : OUT  std_logic;
         data : OUT  std_logic_vector(7 downto 0);
         ready : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal rx_line : std_logic := '0';
   signal clk : std_logic := '0';

 	--Outputs
   signal err : std_logic;
   signal data : std_logic_vector(7 downto 0);
   signal ready : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: rx PORT MAP (
          rx_line => rx_line,
          clk => clk,
          err => err,
          data => data,
          ready => ready
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 3 ns.
      rx_line <= '1';
      wait for 3 ns;	

      --start bit
      rx_line <= '0';
      
      wait for clk_period*16;
      --bit 0
      rx_line <= '0';
      
      wait for clk_period*16;
      --bit 1
      rx_line <= '1';
      
      wait for clk_period*16;
      --bit 2
      rx_line <= '0';
      
      wait for clk_period*16;
      --bit 3
      rx_line <= '1';
      
      wait for clk_period*16;
      --bit 4
      rx_line <= '1';
      
      wait for clk_period*16;
      --bit 5
      rx_line <= '0';
      
      wait for clk_period*16;
      --bit 6
      rx_line <= '1';
      
      wait for clk_period*16;
      --bit 7
      rx_line <= '0';
      
      wait for clk_period*16;
      --stop bit
      rx_line <= '1';
      
      wait for clk_period*16;

      wait;
   end process;

END;