library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;


entity clk_sampler is
	Port ( reset : in  STD_LOGIC;
	       clk :in STD_LOGIC;
	       full : out  STD_LOGIC);
end clk_sampler;

architecture Behavioral of clk_sampler is
	signal counter: unsigned(3 downto 0) :="0000";
begin

	process(clk, reset)
	begin
		if reset = '1' then
			--reset for a half count.
			counter <= "1000";
		elsif rising_edge(clk) then
			counter <= counter + "0001";
		end if;
	end process;

	process(counter)
	begin
		--Full is 1/16 of the incoming frequency
		if counter = "1111" then
			full <= '1';
		else
			full <= '0';
		end if;
	end process;

	process(reset)
	begin
	end process;

end Behavioral;