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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:25:35 11/30/2014 
-- Design Name: 
-- Module Name:    baud_gen - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity baud_gen is
    Port ( clk : in  STD_LOGIC;
           sample_baud : out  STD_LOGIC;
           line_baud : out  STD_LOGIC;
           speed : in  STD_LOGIC);
end baud_gen;

architecture Behavioral of baud_gen is
	signal counter: unsigned := 0 ;
	signal slow_counter: unsigned(4 downto 0) := 0 ;

begin
	process(clk,counter, speed)
	begin
		if rising_edge(clk) then
			counter <= counter + 1;
			if speed = '1' then
				if counter > 312500 then
					counter := 0;
				end if;
				if counter >= 0 and counter <= 156250 then
					sample_baud <= '0';
				else
					sample_baud <= '1';
				end if;
				if counter = 156250 then
					slow_counter <= slow_counter + 1;
				end if;
			else
				if counter > 3125000 then
					counter := 0;
				end if;
				if counter >= 0 and counter <= 1562500 then
					sample_baud <= '0';
				else
					sample_baud <= '1';
				end if;
				if counter = 1562500 then
					slow_counter <= slow_counter + 1;
				end if;
			end if;
		end if;
	end process;
	process(slow_counter)
	begin
		if slow_counter < 16 then
			line_baud <= '0';
		else
			line_baud <= '1';
		end if;
	end process;
end Behavioral;