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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:01:16 10/13/2006 
-- Design Name: 
-- Module Name:    debouncer - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity debouncer is
    Port ( Input : in  STD_LOGIC;
           Clk : in  STD_LOGIC;
           Output : out  STD_LOGIC);
end debouncer;

architecture Behavioral of debouncer is

begin

process (Clk, Input) -- Start a process.

variable count : integer := 0; -- Variable declaration.

begin
	if Clk = '1' and Clk'event then -- Rising edge detection.
		if Input = '1' then 				-- Input is high at clock.
			count := count + 1; 			-- Increment count.
		else 									-- Input low at clock.
			count := 0; 					-- Reset
		end if;
		
		if count > 1000000 then 		-- Input high long enough to
												-- output.
			output <= '1'; 				-- Output high.
		else 									-- Input high long enough.
			output <= '0'; 				-- Output low.
		end if;
	end if;
end process;

end Behavioral;